JP2008146807A5 - - Google Patents

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Publication number
JP2008146807A5
JP2008146807A5 JP2007215679A JP2007215679A JP2008146807A5 JP 2008146807 A5 JP2008146807 A5 JP 2008146807A5 JP 2007215679 A JP2007215679 A JP 2007215679A JP 2007215679 A JP2007215679 A JP 2007215679A JP 2008146807 A5 JP2008146807 A5 JP 2008146807A5
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JP
Japan
Prior art keywords
full adder
adder
carry
dbi
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2007215679A
Other languages
English (en)
Japanese (ja)
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JP2008146807A (ja
Filing date
Publication date
Priority claimed from KR1020060123574A external-priority patent/KR100837812B1/ko
Application filed filed Critical
Publication of JP2008146807A publication Critical patent/JP2008146807A/ja
Publication of JP2008146807A5 publication Critical patent/JP2008146807A5/ja
Ceased legal-status Critical Current

Links

JP2007215679A 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法 Ceased JP2008146807A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060123574A KR100837812B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법

Publications (2)

Publication Number Publication Date
JP2008146807A JP2008146807A (ja) 2008-06-26
JP2008146807A5 true JP2008146807A5 (enExample) 2010-09-30

Family

ID=39497223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007215679A Ceased JP2008146807A (ja) 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法

Country Status (3)

Country Link
US (1) US8010586B2 (enExample)
JP (1) JP2008146807A (enExample)
KR (1) KR100837812B1 (enExample)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100258870B1 (ko) * 1997-12-24 2000-06-15 김영환 2진 비교회로
JP2001034457A (ja) * 1999-07-19 2001-02-09 Toyo Commun Equip Co Ltd 加減算回路
JP2001325093A (ja) * 2000-05-12 2001-11-22 Mitsubishi Electric Corp １ビット比較全加算器、ｎビット比較全加算器、半導体演算装置、およびレイアウトライブラリ
GB0024226D0 (en) 2000-10-04 2000-11-15 Lsi Logic Corp Improvements in or relating to the reduction of simultaneous switching noise in integrated circuits
US6795839B2 (en) * 2000-11-30 2004-09-21 Stmicroelectronics, Inc. Method and device for computing the number of bits set to one in an arbitrary length word
US6665691B2 (en) * 2000-12-08 2003-12-16 Stmicroelectronics, Inc. Circuit for detecting numbers equal to a power of two on a data bus
US6729168B2 (en) * 2000-12-08 2004-05-04 Stmicroelectronics, Inc. Circuit for determining the number of logical one values on a data bus
US6898648B2 (en) * 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US20040068594A1 (en) * 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
JP4319533B2 (ja) * 2003-12-04 2009-08-26 富士通株式会社 ポピュレーションカウント回路
US7411840B2 (en) * 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
KR100578219B1 (ko) 2004-12-30 2006-05-12 주식회사 하이닉스반도체 온-칩 데이터 전송 제어장치 및 그 제어방법
KR100643498B1 (ko) * 2005-11-21 2006-11-10 삼성전자주식회사 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법

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