JP2008146625A5 - - Google Patents

Download PDF

Info

Publication number
JP2008146625A5
JP2008146625A5 JP2007215682A JP2007215682A JP2008146625A5 JP 2008146625 A5 JP2008146625 A5 JP 2008146625A5 JP 2007215682 A JP2007215682 A JP 2007215682A JP 2007215682 A JP2007215682 A JP 2007215682A JP 2008146625 A5 JP2008146625 A5 JP 2008146625A5
Authority
JP
Japan
Prior art keywords
dbi
input
signal
carry
full adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007215682A
Other languages
English (en)
Japanese (ja)
Other versions
JP5124209B2 (ja
JP2008146625A (ja
Filing date
Publication date
Priority claimed from KR1020060123575A external-priority patent/KR100837813B1/ko
Application filed filed Critical
Publication of JP2008146625A publication Critical patent/JP2008146625A/ja
Publication of JP2008146625A5 publication Critical patent/JP2008146625A5/ja
Application granted granted Critical
Publication of JP5124209B2 publication Critical patent/JP5124209B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2007215682A 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法 Active JP5124209B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060123575A KR100837813B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법
KR10-2006-0123575 2006-12-07

Publications (3)

Publication Number Publication Date
JP2008146625A JP2008146625A (ja) 2008-06-26
JP2008146625A5 true JP2008146625A5 (enExample) 2010-09-24
JP5124209B2 JP5124209B2 (ja) 2013-01-23

Family

ID=39497818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007215682A Active JP5124209B2 (ja) 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法

Country Status (3)

Country Link
US (1) US7538698B2 (enExample)
JP (1) JP5124209B2 (enExample)
KR (1) KR100837813B1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100110119A (ko) 2009-04-02 2010-10-12 삼성전자주식회사 데이터를 송신하는 송신기 및 이를 구비하는 반도체 장치
US8260992B2 (en) * 2010-04-12 2012-09-04 Advanced Micro Devices, Inc. Reducing simultaneous switching outputs using data bus inversion signaling
KR102253680B1 (ko) * 2015-01-22 2021-05-21 엘지디스플레이 주식회사 액정표시장치
US10620915B2 (en) * 2018-08-24 2020-04-14 Mediatek Inc. Full adder circuits with reduced delay

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172431A (ja) * 1986-01-24 1987-07-29 Nippon Telegr & Teleph Corp <Ntt> ビツト演算回路
JPH096500A (ja) * 1995-06-16 1997-01-10 Nec Corp インターフェース回路
GB0024226D0 (en) 2000-10-04 2000-11-15 Lsi Logic Corp Improvements in or relating to the reduction of simultaneous switching noise in integrated circuits
TW507128B (en) * 2001-07-12 2002-10-21 Via Tech Inc Data memory controller supporting the data bus invert
US6898648B2 (en) 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
JP2004080553A (ja) * 2002-08-21 2004-03-11 Nec Corp データ出力回路及びデータ出力方法
US20040068594A1 (en) * 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
JP4319533B2 (ja) * 2003-12-04 2009-08-26 富士通株式会社 ポピュレーションカウント回路
US7411840B2 (en) 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
KR100621353B1 (ko) 2005-11-08 2006-09-07 삼성전자주식회사 데이터 반전 확인 기능을 가지는 데이터 입출력 회로 및이를 포함하는 반도체 메모리 장치
KR100643498B1 (ko) 2005-11-21 2006-11-10 삼성전자주식회사 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법

Similar Documents

Publication Publication Date Title
JP2010511250A5 (enExample)
Low et al. A new approach to the design of efficient residue generators for arbitrary moduli
Roy et al. Tile before multiplication: An efficient strategy to optimize DSP multiplier for accelerating prime field ECC for NIST curves
JP5165755B2 (ja) 有限体演算を用いる暗号学的乱数発生器
JP2010531018A5 (enExample)
JP2008146625A5 (enExample)
Kumar et al. 4-2 Compressor design with new XOR-XNOR module
CN112737778B (zh) 数字签名生成、验证方法及装置、电子设备及存储介质
JP3033212B2 (ja) 乗算器
JP5124209B2 (ja) 半導体集積回路のｄｂｉ信号生成装置および方法
CN104750455B (zh) 一种基于蒙哥马利模乘的数据处理方法和装置
Ravi et al. Low power and efficient dadda multiplier
TWI447412B (zh) 測試模式訊號系統以及傳送測試模式訊號的方法
JP2008146807A5 (enExample)
Sekanina et al. Two-step evolution of polymorphic circuits for image multi-filtering
JP4956295B2 (ja) 半導体記憶装置
US20110019814A1 (en) Variable sized hash output generation using a single hash and mixing function
KR101904142B1 (ko) 테스트 모드 신호 생성 회로
CN108683425A (zh) 一种bch译码器
JPH01220528A (ja) パリテイ発生器
US8010586B2 (en) Apparatus and method of generating DBI signal in semiconductor integrated circuit
US7472154B2 (en) Multiplication remainder calculator
US20230214182A1 (en) Adder with first and second adder circuits for non-power of two input width
Kocak et al. Design and implementation of high-performance high-valency ling adders
KR101764343B1 (ko) 여분 기저 기반의 유한체상 곱셈 장치 및 방법