KR100837813B1 - 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법 - Google Patents

반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법 Download PDF

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Publication number
KR100837813B1
KR100837813B1 KR1020060123575A KR20060123575A KR100837813B1 KR 100837813 B1 KR100837813 B1 KR 100837813B1 KR 1020060123575 A KR1020060123575 A KR 1020060123575A KR 20060123575 A KR20060123575 A KR 20060123575A KR 100837813 B1 KR100837813 B1 KR 100837813B1
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South Korea
Prior art keywords
dbi
carry
signal
data
full adder
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KR1020060123575A
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Korean (ko)
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KR20080051840A (ko
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신범주
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주식회사 하이닉스반도체
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Priority to KR1020060123575A priority Critical patent/KR100837813B1/ko
Priority to US11/826,765 priority patent/US7538698B2/en
Priority to JP2007215682A priority patent/JP5124209B2/ja
Publication of KR20080051840A publication Critical patent/KR20080051840A/ko
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Publication of KR100837813B1 publication Critical patent/KR100837813B1/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020060123575A 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법 Active KR100837813B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020060123575A KR100837813B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법
US11/826,765 US7538698B2 (en) 2006-12-07 2007-07-18 Apparatus and method of generating DBI signal in semiconductor integrated circuit
JP2007215682A JP5124209B2 (ja) 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060123575A KR100837813B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법

Publications (2)

Publication Number Publication Date
KR20080051840A KR20080051840A (ko) 2008-06-11
KR100837813B1 true KR100837813B1 (ko) 2008-06-13

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Country Link
US (1) US7538698B2 (enExample)
JP (1) JP5124209B2 (enExample)
KR (1) KR100837813B1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160090989A (ko) * 2015-01-22 2016-08-02 엘지디스플레이 주식회사 액정표시장치

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100110119A (ko) 2009-04-02 2010-10-12 삼성전자주식회사 데이터를 송신하는 송신기 및 이를 구비하는 반도체 장치
US8260992B2 (en) * 2010-04-12 2012-09-04 Advanced Micro Devices, Inc. Reducing simultaneous switching outputs using data bus inversion signaling
US10620915B2 (en) * 2018-08-24 2020-04-14 Mediatek Inc. Full adder circuits with reduced delay

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121918A1 (en) 2000-10-04 2002-09-05 Alani Alaa F. Reducing the effect of simultaneous switching noise
KR100621353B1 (ko) 2005-11-08 2006-09-07 삼성전자주식회사 데이터 반전 확인 기능을 가지는 데이터 입출력 회로 및이를 포함하는 반도체 메모리 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172431A (ja) * 1986-01-24 1987-07-29 Nippon Telegr & Teleph Corp <Ntt> ビツト演算回路
JPH096500A (ja) * 1995-06-16 1997-01-10 Nec Corp インターフェース回路
TW507128B (en) * 2001-07-12 2002-10-21 Via Tech Inc Data memory controller supporting the data bus invert
US6898648B2 (en) 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
JP2004080553A (ja) * 2002-08-21 2004-03-11 Nec Corp データ出力回路及びデータ出力方法
US20040068594A1 (en) * 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
JP4319533B2 (ja) * 2003-12-04 2009-08-26 富士通株式会社 ポピュレーションカウント回路
US7411840B2 (en) 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
KR100643498B1 (ko) 2005-11-21 2006-11-10 삼성전자주식회사 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121918A1 (en) 2000-10-04 2002-09-05 Alani Alaa F. Reducing the effect of simultaneous switching noise
KR100621353B1 (ko) 2005-11-08 2006-09-07 삼성전자주식회사 데이터 반전 확인 기능을 가지는 데이터 입출력 회로 및이를 포함하는 반도체 메모리 장치

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160090989A (ko) * 2015-01-22 2016-08-02 엘지디스플레이 주식회사 액정표시장치
KR102253680B1 (ko) * 2015-01-22 2021-05-21 엘지디스플레이 주식회사 액정표시장치

Also Published As

Publication number Publication date
JP5124209B2 (ja) 2013-01-23
JP2008146625A (ja) 2008-06-26
KR20080051840A (ko) 2008-06-11
US7538698B2 (en) 2009-05-26
US20080137445A1 (en) 2008-06-12

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