KR100813533B1 - 반도체 메모리 장치 및 그 데이터 마스크 방법 - Google Patents

반도체 메모리 장치 및 그 데이터 마스크 방법 Download PDF

Info

Publication number
KR100813533B1
KR100813533B1 KR1020060088742A KR20060088742A KR100813533B1 KR 100813533 B1 KR100813533 B1 KR 100813533B1 KR 1020060088742 A KR1020060088742 A KR 1020060088742A KR 20060088742 A KR20060088742 A KR 20060088742A KR 100813533 B1 KR100813533 B1 KR 100813533B1
Authority
KR
South Korea
Prior art keywords
mask information
data
memory cell
registers
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020060088742A
Other languages
English (en)
Korean (ko)
Inventor
윤상식
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060088742A priority Critical patent/KR100813533B1/ko
Priority to US11/646,449 priority patent/US7590009B2/en
Priority to TW096111881A priority patent/TWI336478B/zh
Priority to CN2007100969617A priority patent/CN101145384B/zh
Priority to JP2007223963A priority patent/JP5064939B2/ja
Application granted granted Critical
Publication of KR100813533B1 publication Critical patent/KR100813533B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
KR1020060088742A 2006-09-13 2006-09-13 반도체 메모리 장치 및 그 데이터 마스크 방법 Expired - Fee Related KR100813533B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020060088742A KR100813533B1 (ko) 2006-09-13 2006-09-13 반도체 메모리 장치 및 그 데이터 마스크 방법
US11/646,449 US7590009B2 (en) 2006-09-13 2006-12-28 Semiconductor memory apparatus and data masking method of the same
TW096111881A TWI336478B (en) 2006-09-13 2007-04-03 Semiconductor memory apparatus and data masking method of the same
CN2007100969617A CN101145384B (zh) 2006-09-13 2007-04-19 半导体存储器装置及其数据掩蔽方法
JP2007223963A JP5064939B2 (ja) 2006-09-13 2007-08-30 半導体メモリ装置及びそのデータマスキング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060088742A KR100813533B1 (ko) 2006-09-13 2006-09-13 반도체 메모리 장치 및 그 데이터 마스크 방법

Publications (1)

Publication Number Publication Date
KR100813533B1 true KR100813533B1 (ko) 2008-03-17

Family

ID=39169481

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060088742A Expired - Fee Related KR100813533B1 (ko) 2006-09-13 2006-09-13 반도체 메모리 장치 및 그 데이터 마스크 방법

Country Status (5)

Country Link
US (1) US7590009B2 (enExample)
JP (1) JP5064939B2 (enExample)
KR (1) KR100813533B1 (enExample)
CN (1) CN101145384B (enExample)
TW (1) TWI336478B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101090329B1 (ko) * 2010-02-25 2011-12-07 주식회사 하이닉스반도체 메모리장치, 메모리장치의 동작방법 및 제어방법

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8006033B2 (en) * 2008-09-09 2011-08-23 Intel Corporation Systems, methods, and apparatuses for in-band data mask bit transmission
EP3422178B1 (en) * 2011-04-01 2023-02-15 Intel Corporation Vector friendly instruction format and execution thereof
CN104011670B (zh) 2011-12-22 2016-12-28 英特尔公司 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令
US20140068227A1 (en) * 2011-12-22 2014-03-06 Bret L. Toll Systems, apparatuses, and methods for extracting a writemask from a register
US9135984B2 (en) * 2013-12-18 2015-09-15 Micron Technology, Inc. Apparatuses and methods for writing masked data to a buffer
US10296489B2 (en) 2014-12-27 2019-05-21 Intel Corporation Method and apparatus for performing a vector bit shuffle
US10063474B2 (en) 2015-09-29 2018-08-28 Keysight Technologies Singapore (Holdings) Pte Ltd Parallel match processing of network packets to identify packet data for masking or other actions
KR20170068718A (ko) * 2015-12-09 2017-06-20 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007060A (ja) * 2001-06-26 2003-01-10 Toshiba Microelectronics Corp 半導体記憶装置及びその制御方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0554651A (ja) * 1991-08-29 1993-03-05 Nec Corp 半導体メモリ回路
JPH08249884A (ja) * 1995-03-08 1996-09-27 Sanyo Electric Co Ltd 半導体メモリのライトパービット回路
KR0183173B1 (ko) * 1995-12-13 1999-05-15 윤종용 버퍼 메모리 제어 장치
JP3003613B2 (ja) * 1997-01-31 2000-01-31 日本電気株式会社 半導体記憶装置
WO1999019805A1 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
KR100360408B1 (ko) 2000-09-16 2002-11-13 삼성전자 주식회사 독출동작시 데이터 스트로브 신호와 동일한 신호를출력하는 데이터 마스킹핀을 갖는 반도체 메모리장치 및이를 구비하는 메모리 시스템
DE10128770B4 (de) 2001-06-13 2014-05-15 Qimonda Ag Verfahren zum Übertragen von Daten in ein Speicherzellenfeld und Schaltungsanordnung
KR100427037B1 (ko) 2001-09-24 2004-04-14 주식회사 하이닉스반도체 적응적 출력 드라이버를 갖는 반도체 기억장치
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
JP4492938B2 (ja) 2004-05-26 2010-06-30 ルネサスエレクトロニクス株式会社 半導体記憶装置及びその動作方法
JP2007242162A (ja) * 2006-03-09 2007-09-20 Toshiba Corp 半導体記憶装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007060A (ja) * 2001-06-26 2003-01-10 Toshiba Microelectronics Corp 半導体記憶装置及びその制御方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101090329B1 (ko) * 2010-02-25 2011-12-07 주식회사 하이닉스반도체 메모리장치, 메모리장치의 동작방법 및 제어방법

Also Published As

Publication number Publication date
CN101145384B (zh) 2010-05-26
JP2008071477A (ja) 2008-03-27
US20080062771A1 (en) 2008-03-13
TW200814091A (en) 2008-03-16
JP5064939B2 (ja) 2012-10-31
US7590009B2 (en) 2009-09-15
CN101145384A (zh) 2008-03-19
TWI336478B (en) 2011-01-21

Similar Documents

Publication Publication Date Title
JP5064939B2 (ja) 半導体メモリ装置及びそのデータマスキング方法
JP5086709B2 (ja) データ入出力エラー検出機能を有する半導体メモリ装置
KR100945968B1 (ko) 반도체기억장치
KR100295046B1 (ko) 개선된싱크로너스디램과로직이하나의칩에병합된반도체장치
US7765442B2 (en) Memory device testable without using data and dataless test method
JP2010073300A (ja) 半導体メモリ装置
JP2006127653A (ja) メモリ素子
JP2004362762A (ja) テストモードにおいて低い転送速度でデータビットを出力するｉｃメモリ装置及びその動作方法
JP4903481B2 (ja) メモリ装置の構造
KR100564033B1 (ko) 단일 버퍼 선택 입력 단자를 가지는 반도체 메모리 및반도체 메모리 테스트 방법
US6292419B2 (en) Synchronous semiconductor memory device
JP3735699B2 (ja) 高速半導体メモリ装置の入出力回路及びその高速半導体メモリ装置
JP2001243797A (ja) 半導体装置及びその試験方法
KR20040089188A (ko) 상대 어드레스 방식으로 모든 메모리 셀들의 액세스가가능하게 하는 반도체 메모리 장치
KR20050011318A (ko) Ｄｑ 인터리브드 데이터 액세스 테스트 방식에 따라동작하는 데이터 입출력 회로를 구비하는 반도체메모리장치 및 이의 데이터 입출력 방법
US7031201B2 (en) Semiconductor memory device with late write function and data input/output method therefor
KR100800133B1 (ko) 디큐 압축 테스트 모드를 위한 디큐 압축 방법 및 그 회로
KR100596450B1 (ko) 동작모드에 따라 데이터 스트로브 타입을 선택적으로사용할 수 있는 반도체 메모리 장치
JP3038618B2 (ja) テスト用回路を内蔵したメモリ装置
KR100680457B1 (ko) 난드 플래시 메모리 소자의 데이터 출력 회로 및 이를이용한 데이터 출력 방법
KR20000059845A (ko) 데이터 독출 억세스 시간이 최소화된 고속 메모리장치
JP2007018710A (ja) 半導体装置及びその試験方法
KR20120012140A (ko) 반도체 메모리 장치 및 그 동작 방법
JPS5826391A (ja) 出力レジスタ付き記憶素子
JPH03152487A (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

G170 Re-publication after modification of scope of protection [patent]
PG1701 Publication of correction

St.27 status event code: A-5-5-P10-P19-oth-PG1701

Patent document republication publication date: 20080408

Republication note text: Request for Correction Notice (Document Request)

Gazette number: 1008135330000

Gazette reference publication date: 20080317

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20120222

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20130308

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20130308

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301