TWI336478B - Semiconductor memory apparatus and data masking method of the same - Google Patents
Semiconductor memory apparatus and data masking method of the same Download PDFInfo
- Publication number
- TWI336478B TWI336478B TW096111881A TW96111881A TWI336478B TW I336478 B TWI336478 B TW I336478B TW 096111881 A TW096111881 A TW 096111881A TW 96111881 A TW96111881 A TW 96111881A TW I336478 B TWI336478 B TW I336478B
- Authority
- TW
- Taiwan
- Prior art keywords
- mask information
- data
- mask
- semiconductor memory
- memory device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000000034 method Methods 0.000 title claims description 17
- 230000000873 masking effect Effects 0.000 title claims description 14
- 230000004044 response Effects 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 101150052205 wrm-1 gene Proteins 0.000 description 2
- 206010011469 Crying Diseases 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060088742A KR100813533B1 (ko) | 2006-09-13 | 2006-09-13 | 반도체 메모리 장치 및 그 데이터 마스크 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200814091A TW200814091A (en) | 2008-03-16 |
| TWI336478B true TWI336478B (en) | 2011-01-21 |
Family
ID=39169481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW096111881A TWI336478B (en) | 2006-09-13 | 2007-04-03 | Semiconductor memory apparatus and data masking method of the same |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7590009B2 (enExample) |
| JP (1) | JP5064939B2 (enExample) |
| KR (1) | KR100813533B1 (enExample) |
| CN (1) | CN101145384B (enExample) |
| TW (1) | TWI336478B (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8006033B2 (en) * | 2008-09-09 | 2011-08-23 | Intel Corporation | Systems, methods, and apparatuses for in-band data mask bit transmission |
| KR101090329B1 (ko) * | 2010-02-25 | 2011-12-07 | 주식회사 하이닉스반도체 | 메모리장치, 메모리장치의 동작방법 및 제어방법 |
| EP3422178B1 (en) * | 2011-04-01 | 2023-02-15 | Intel Corporation | Vector friendly instruction format and execution thereof |
| CN104011670B (zh) | 2011-12-22 | 2016-12-28 | 英特尔公司 | 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令 |
| US20140068227A1 (en) * | 2011-12-22 | 2014-03-06 | Bret L. Toll | Systems, apparatuses, and methods for extracting a writemask from a register |
| US9135984B2 (en) * | 2013-12-18 | 2015-09-15 | Micron Technology, Inc. | Apparatuses and methods for writing masked data to a buffer |
| US10296489B2 (en) | 2014-12-27 | 2019-05-21 | Intel Corporation | Method and apparatus for performing a vector bit shuffle |
| US10063474B2 (en) | 2015-09-29 | 2018-08-28 | Keysight Technologies Singapore (Holdings) Pte Ltd | Parallel match processing of network packets to identify packet data for masking or other actions |
| KR20170068718A (ko) * | 2015-12-09 | 2017-06-20 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0554651A (ja) * | 1991-08-29 | 1993-03-05 | Nec Corp | 半導体メモリ回路 |
| JPH08249884A (ja) * | 1995-03-08 | 1996-09-27 | Sanyo Electric Co Ltd | 半導体メモリのライトパービット回路 |
| KR0183173B1 (ko) * | 1995-12-13 | 1999-05-15 | 윤종용 | 버퍼 메모리 제어 장치 |
| JP3003613B2 (ja) * | 1997-01-31 | 2000-01-31 | 日本電気株式会社 | 半導体記憶装置 |
| WO1999019805A1 (en) * | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Method and apparatus for two step memory write operations |
| KR100360408B1 (ko) | 2000-09-16 | 2002-11-13 | 삼성전자 주식회사 | 독출동작시 데이터 스트로브 신호와 동일한 신호를출력하는 데이터 마스킹핀을 갖는 반도체 메모리장치 및이를 구비하는 메모리 시스템 |
| DE10128770B4 (de) | 2001-06-13 | 2014-05-15 | Qimonda Ag | Verfahren zum Übertragen von Daten in ein Speicherzellenfeld und Schaltungsanordnung |
| JP2003007060A (ja) * | 2001-06-26 | 2003-01-10 | Toshiba Microelectronics Corp | 半導体記憶装置及びその制御方法 |
| KR100427037B1 (ko) | 2001-09-24 | 2004-04-14 | 주식회사 하이닉스반도체 | 적응적 출력 드라이버를 갖는 반도체 기억장치 |
| US7308524B2 (en) * | 2003-01-13 | 2007-12-11 | Silicon Pipe, Inc | Memory chain |
| JP4492938B2 (ja) | 2004-05-26 | 2010-06-30 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置及びその動作方法 |
| JP2007242162A (ja) * | 2006-03-09 | 2007-09-20 | Toshiba Corp | 半導体記憶装置 |
-
2006
- 2006-09-13 KR KR1020060088742A patent/KR100813533B1/ko not_active Expired - Fee Related
- 2006-12-28 US US11/646,449 patent/US7590009B2/en not_active Expired - Fee Related
-
2007
- 2007-04-03 TW TW096111881A patent/TWI336478B/zh not_active IP Right Cessation
- 2007-04-19 CN CN2007100969617A patent/CN101145384B/zh not_active Expired - Fee Related
- 2007-08-30 JP JP2007223963A patent/JP5064939B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101145384B (zh) | 2010-05-26 |
| JP2008071477A (ja) | 2008-03-27 |
| US20080062771A1 (en) | 2008-03-13 |
| TW200814091A (en) | 2008-03-16 |
| KR100813533B1 (ko) | 2008-03-17 |
| JP5064939B2 (ja) | 2012-10-31 |
| US7590009B2 (en) | 2009-09-15 |
| CN101145384A (zh) | 2008-03-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |