KR100701861B1 - 강유전체 막의 형성 방법, 강유전체 메모리, 강유전체메모리의 제조 방법, 반도체 장치, 및 반도체 장치의 제조방법 - Google Patents
강유전체 막의 형성 방법, 강유전체 메모리, 강유전체메모리의 제조 방법, 반도체 장치, 및 반도체 장치의 제조방법 Download PDFInfo
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Abstract
Description
Claims (23)
- 기판 상에 형성된 비정질의 산화물 막에 펄스 형상의 레이저 광 또는 램프 광을 조사하여 산화물의 미결정핵(microcrystal nuclei)을 형성하는 것,미결정핵을 포함하는 산화물 막 상에 광 투과/흡수막을 형성하는 것,광 투과/흡수막의 상부로부터 펄스 형상의 레이저 광 또는 램프 광을 조사하여 산화물을 결정화시켜서 강유전체를 형성하는 것을 포함하는, 강유전체 막의 형성 방법.
- 기판 상에 형성된 비정질의 산화물 막의 소정 부분에만 펄스 형상의 레이저 광을 조사하여 산화물의 미결정핵을 형성하는 것,미결정핵을 포함하는 산화물 막 상에 광 투과/흡수막을 형성하는 것,광 투과/흡수막의 상부로부터 펄스 형상의 램프 광을 조사하여 소정 부분의 산화물을 결정화시켜서 강유전체를 형성하는 것을 포함하는, 강유전체 막의 형성 방법.
- 기판 상에 형성된 비정질의 산화물 막에 펄스 형상의 램프 광을 조사하여 산화물의 미결정핵을 형성하는 것,미결정핵을 포함하는 산화물 막 상에 광 투과/흡수막을 형성하는 것,광 투과/흡수막의 상부로부터 소정 부분에만 펄스 형상의 레이저 광을 조사 하여 소정 부분의 산화물을 결정화시켜서 강유전체를 형성하는 것을 포함하는, 강유전체 막의 형성 방법.
- 기판 상에 형성된 비정질의 산화물 막에 펄스 형상의 레이저 광 또는 램프 광을 조사하는 것,그 후에 산화물 막 상에 광 투과/흡수막을 형성하는 것,광 투과/흡수막의 상부로부터 펄스 형상의 레이저 광 또는 램프 광을 조사하여 산화물을 결정화시켜서 강유전체를 형성하는 것을 포함하는, 강유전체 막의 형성 방법.
- 제2항 또는 제3항에 있어서,광 투과/흡수막 중 산화물 막의 소정 부분의 위쪽의 영역이 노출되도록 광 투과/흡수막 상에 광 차단막을 형성하는 것을 포함하는, 강유전체 막의 형성 방법.
- 제2항 또는 제3항에 있어서,광 투과/흡수막은, 산화물 막의 소정 부분 상에만 형성되고,산화물 막 상에 광 투과/흡수막을 피해서 광 차단막을 형성하는 것을 포함하는, 강유전체 막의 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 있어서,광 투과/흡수막은, 산화물 도전체를 이용하여 형성되는, 강유전체 막의 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 있어서,기판상에 광 반사막을 형성하고, 광 반사막의 위쪽에 비정질의 산화물막을 형성하는, 강유전체 막의 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 있어서,비정질의 산화물 막에 조사되는 광의 강도와, 산화물을 결정화하기 위해서 조사되는 광의 강도가 다른, 강유전체 막의 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 있어서,비정질의 산화물 막에 조사되는 광의 펄스 수와, 산화물을 결정화하기 위해서 조사되는 광의 펄스 수가 다른, 강유전체 막의 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 있어서,상기 강유전체는, 페로브스카이트형 결정 구조를 갖는, 강유전체 막의 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 있어서,상기 강유전체는, 층상 페로브스카이트형 결정 구조를 갖는, 강유전체 막의 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 기재된 강유전체 막의 형성 방법을 이용하여 강유전체 층을 형성하는 것을 포함하는, 강유전체 메모리의 제조 방법.
- 제1항 내지 제3항 중 어느 한 항에 기재된 강유전체막의 형성 방법을 이용하여 강유전체층을 형성하며,강유전체 층을 형성할 때에는,적어도 미결정핵을 포함하는 산화물 막을 에칭하는 것을 포함하고,에칭은, 적어도 산화물을 결정화시키기 전에 행해지는, 강유전체 메모리의 제조 방법.
- 제13항에 있어서,강유전체 층을 형성할 때에, 강유전체 층 상에 설치되는 광 투과/흡수막을 전극으로서 형성하는, 강유전체 메모리의 제조 방법.
- 제13항에 기재된 강유전체 메모리의 제조 방법에 의해서 형성되는, 강유전체 메모리.
- 제16항에 있어서,강유전체 층의 주변에 배치되는 절연층이 산화물의 미결정핵을 갖는, 강유전체 메모리.
- 제16항에 있어서,강유전체 층 아래에 배치되는 전극이 광을 반사하는 성질을 갖는, 강유전체 메모리.
- 삭제
- 메모리 셀 어레이가, 스트라이프 형상으로 형성되고, 또한 교차하도록 배치되는 다수의 하부 전극과 상부 전극; 및 하부 전극과 상부 전극 사이에서 하부 전극과 상부 전극의 적어도 교차 부분에 배치되는 강유전체 층을 포함하며, 인접하는 메모리 셀 어레이 사이의 교차 부분이 겹치지 않도록, 각 메모리 셀 어레이의 하부 전극과 상부 전극이 배치되는 강유전체 메모리의 제조 방법으로서,상기 강유전체 메모리에 포함되는 다수의 메모리 셀 어레이의 상부 전극을 광 투과/흡수막으로서 형성하고,강유전체 메모리의 강유전체 층을 제1항 내지 제4항 중 어느 한 항에 기재된 강유전체 막의 형성 방법에 의해서 형성하는, 강유전체 메모리의 제조 방법.
- 제20항에 있어서,적어도 2 이상의 메모리 셀 어레이를 적층한 후에, 각 메모리 셀 어레이에서 산화물 막을 결정화시켜서 강유전체 층을 형성하는, 강유전체 메모리의 제조 방법.
- 강유전체 층을 갖는 메모리 셀 영역과 그 밖의 회로 영역을 포함하는 반도체 장치의 제조 방법에 있어서,기판 상의 소정의 영역에 메모리 셀 영역을 형성하는 것,기판 상의 메모리 셀 영역과 다른 부분에 회로 영역을 형성하는 것을 포함하고,회로 영역을 형성할 때에는, 회로 영역 상에 광 차단막을 형성하는 것을 포함하며,메모리 셀 영역을 형성할 때에는, 적어도 회로 영역 상에 광 차단막을 형성한 후에 제13항에 기재의 강유전체 메모리의 제조 방법에 의해서 상기 강유전체 층을 형성하는, 반도체 장치의 제조 방법.
- 강유전체 층을 갖는 메모리 셀 영역과, 메모리 셀 영역과 기판 상의 다른 영역에 배치되는 그 밖의 회로 영역을 포함하고,제22항에 기재된 반도체 장치의 제조 방법을 이용하여 형성되는, 반도체 장치.
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JPJP-P-2002-00095058 | 2002-03-29 | ||
JP2002095058A JP2003298021A (ja) | 2002-03-29 | 2002-03-29 | 強誘電体薄膜の形成方法、強誘電体メモリならびに強誘電体メモリの製造方法、および半導体装置ならびに半導体装置の製造方法 |
PCT/JP2003/003961 WO2003083946A1 (fr) | 2002-03-29 | 2003-03-28 | Procede de formation de film ferroelectrique, memoire ferroelectrique et procede de production correspondant, dispositif semi-conducteur et procede de production correspondant |
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JP (1) | JP2003298021A (ko) |
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JP2004158487A (ja) | 2002-11-01 | 2004-06-03 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US7247503B2 (en) * | 2003-05-07 | 2007-07-24 | Macronix International Co., Ltd. | Method of laser annealing to form an epitaxial growth layer |
JP2005136071A (ja) * | 2003-10-29 | 2005-05-26 | Seiko Epson Corp | クロスポイント型強誘電体メモリ |
US7633424B1 (en) * | 2006-06-08 | 2009-12-15 | Skyworks Solutions, Inc. | Wide temperature range dielectric absorber |
KR20080010900A (ko) * | 2006-07-28 | 2008-01-31 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법 |
KR100763918B1 (ko) * | 2006-07-28 | 2007-10-05 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
KR101169396B1 (ko) * | 2006-12-22 | 2012-07-30 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 동작 방법 |
JP4963062B2 (ja) * | 2006-12-26 | 2012-06-27 | 独立行政法人産業技術総合研究所 | Aサイト層状秩序化型ペロブスカイトMn酸化物薄膜の製造方法 |
KR101038347B1 (ko) * | 2008-10-24 | 2011-05-31 | 김성년 | 송풍기 |
CN107251254B (zh) * | 2015-02-17 | 2020-01-21 | 株式会社理光 | 晶体图案形成方法、压电膜制造方法、压电元件制造方法及液体排放头制造方法 |
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US5375085A (en) * | 1992-09-30 | 1994-12-20 | Texas Instruments Incorporated | Three-dimensional ferroelectric integrated circuit without insulation layer between memory layers |
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US397315A (en) * | 1889-02-05 | shttrtleff | ||
US5519234A (en) * | 1991-02-25 | 1996-05-21 | Symetrix Corporation | Ferroelectric dielectric memory cell can switch at least giga cycles and has low fatigue - has high dielectric constant and low leakage current |
US5188902A (en) * | 1991-05-30 | 1993-02-23 | Northern Illinois University | Production of PT/PZT/PLZI thin films, powders, and laser `direct write` patterns |
JP3206105B2 (ja) | 1992-06-09 | 2001-09-04 | セイコーエプソン株式会社 | 誘電体素子の製造方法及び半導体記憶装置 |
US5372859A (en) * | 1992-10-20 | 1994-12-13 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment |
JP3286002B2 (ja) | 1993-03-25 | 2002-05-27 | オリンパス光学工業株式会社 | 薄膜形成装置 |
JPH07320539A (ja) | 1994-05-24 | 1995-12-08 | Sumitomo Electric Ind Ltd | 誘電体薄膜の製造方法 |
KR100318457B1 (ko) * | 1998-10-28 | 2002-02-19 | 박종섭 | 플라즈마를이용한강유전체박막형성방법 |
JP2000144419A (ja) | 1998-11-12 | 2000-05-26 | Matsushita Electric Ind Co Ltd | 誘電体薄膜の製造方法 |
JP2001094064A (ja) | 1999-09-20 | 2001-04-06 | Toshiba Corp | 結晶化方法及び半導体装置の製造方法 |
JP3664033B2 (ja) * | 2000-03-29 | 2005-06-22 | セイコーエプソン株式会社 | セラミックスの製造方法およびその製造装置 |
JP4299959B2 (ja) | 2000-08-14 | 2009-07-22 | 株式会社東芝 | 半導体装置の製造方法 |
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