KR100525137B1 - 반도체 장치 및 그 동작 방법 - Google Patents

반도체 장치 및 그 동작 방법 Download PDF

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Publication number
KR100525137B1
KR100525137B1 KR10-2002-0065131A KR20020065131A KR100525137B1 KR 100525137 B1 KR100525137 B1 KR 100525137B1 KR 20020065131 A KR20020065131 A KR 20020065131A KR 100525137 B1 KR100525137 B1 KR 100525137B1
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KR
South Korea
Prior art keywords
memory cell
bit line
memory
memory cells
bit lines
Prior art date
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Expired - Fee Related
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KR10-2002-0065131A
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English (en)
Korean (ko)
Other versions
KR20030034016A (ko
Inventor
다께우찌유지
시로따리이찌로
Original Assignee
가부시끼가이샤 도시바
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Publication of KR20030034016A publication Critical patent/KR20030034016A/ko
Application granted granted Critical
Publication of KR100525137B1 publication Critical patent/KR100525137B1/ko
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
KR10-2002-0065131A 2001-10-24 2002-10-24 반도체 장치 및 그 동작 방법 Expired - Fee Related KR100525137B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2001-00326900 2001-10-24
JP2001326900 2001-10-24
JP2002027436A JP4004809B2 (ja) 2001-10-24 2002-02-04 半導体装置及びその動作方法
JPJP-P-2002-00027436 2002-02-04

Publications (2)

Publication Number Publication Date
KR20030034016A KR20030034016A (ko) 2003-05-01
KR100525137B1 true KR100525137B1 (ko) 2005-11-02

Family

ID=26624079

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0065131A Expired - Fee Related KR100525137B1 (ko) 2001-10-24 2002-10-24 반도체 장치 및 그 동작 방법

Country Status (3)

Country Link
US (2) US6806525B2 (enExample)
JP (1) JP4004809B2 (enExample)
KR (1) KR100525137B1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7339822B2 (en) * 2002-12-06 2008-03-04 Sandisk Corporation Current-limited latch
KR100582335B1 (ko) * 2003-12-05 2006-05-22 에스티마이크로일렉트로닉스 엔.브이. 낸드 플래시 소자의 제조 방법
US7187059B2 (en) * 2004-06-24 2007-03-06 International Business Machines Corporation Compressive SiGe <110> growth and structure of MOSFET devices
KR100729351B1 (ko) * 2004-12-31 2007-06-15 삼성전자주식회사 낸드 플래시 메모리 장치 및 그것의 프로그램 방법
JP4580787B2 (ja) 2005-03-16 2010-11-17 株式会社東芝 半導体記憶装置およびその形成方法
US8314024B2 (en) 2008-12-19 2012-11-20 Unity Semiconductor Corporation Device fabrication
US7751242B2 (en) * 2005-08-30 2010-07-06 Micron Technology, Inc. NAND memory device and programming methods
WO2007069305A1 (ja) * 2005-12-14 2007-06-21 Fujitsu Limited 半導体装置とその製造方法
KR100666223B1 (ko) * 2006-02-22 2007-01-09 삼성전자주식회사 메모리셀 사이의 커플링 노이즈를 저감시키는 3-레벨불휘발성 반도체 메모리 장치 및 이에 대한 구동방법
US7638878B2 (en) * 2006-04-13 2009-12-29 Micron Technology, Inc. Devices and systems including the bit lines and bit line contacts
JP2008047219A (ja) * 2006-08-16 2008-02-28 Toshiba Corp Ｎａｎｄ型フラッシュメモリ
JP5072301B2 (ja) * 2006-09-25 2012-11-14 株式会社東芝 半導体集積回路装置及びその動作方法
EP2094537B1 (en) * 2006-12-06 2013-02-27 Dow Corning Corporation Airbag and process for its assembly
US7638822B1 (en) 2007-01-03 2009-12-29 Xilinx, Inc. Memory cell with single-event-upset tolerance
US7515452B1 (en) * 2007-01-03 2009-04-07 Xilinx, Inc. Interleaved memory cell with single-event-upset tolerance
US7688612B2 (en) * 2007-04-13 2010-03-30 Aplus Flash Technology, Inc. Bit line structure for a multilevel, dual-sided nonvolatile memory cell array
JP4703669B2 (ja) 2008-02-18 2011-06-15 株式会社東芝 半導体記憶装置及びその製造方法
WO2009143090A2 (en) * 2008-05-22 2009-11-26 Dow Corning Corporation Process and composition for fabricating non-sewn seams
JP4770930B2 (ja) * 2009-01-21 2011-09-14 ソニー株式会社 クロスポイント型半導体メモリ装置及びその製造方法
JP2011181131A (ja) 2010-02-26 2011-09-15 Toshiba Corp 半導体記憶装置
JP2012204537A (ja) * 2011-03-24 2012-10-22 Toshiba Corp 半導体記憶装置およびその製造方法
KR102291518B1 (ko) 2015-03-20 2021-08-20 삼성전자주식회사 불휘발성 메모리 장치 및 불휘발성 메모리 장치를 포함하는 스토리지 장치
US11020140B2 (en) 2015-06-17 2021-06-01 Cilag Gmbh International Ultrasonic surgical blade for use with ultrasonic surgical instruments

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000017357A (ko) * 1998-08-18 2000-03-25 가네꼬 히사시 반도체 기억 장치
JP2000188384A (ja) * 1998-12-22 2000-07-04 Toshiba Corp 不揮発性半導体記憶装置
JP2001028196A (ja) * 1999-05-12 2001-01-30 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
US6188608B1 (en) * 1999-04-23 2001-02-13 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3210355B2 (ja) 1991-03-04 2001-09-17 株式会社東芝 不揮発性半導体記憶装置
JPH06215564A (ja) * 1993-01-13 1994-08-05 Nec Corp 半導体記憶装置
JP3789173B2 (ja) * 1996-07-22 2006-06-21 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及び半導体記憶装置のアクセス方法
KR100261221B1 (ko) * 1997-12-31 2000-07-01 윤종용 단일 트랜지스터 셀 및 이를 제조하는 방법 및 이 소자로 구성된 메모리 회로와 이를 구동하는 방법
JP3629144B2 (ja) * 1998-06-01 2005-03-16 株式会社東芝 不揮発性半導体記憶装置
EP1225595B1 (en) * 2001-01-15 2007-08-08 STMicroelectronics S.r.l. Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell
DE60218812D1 (de) * 2001-12-28 2007-04-26 St Microelectronics Srl Verfahren zur Regulierung der Sourcespannung während der Programmierung einer nichtflüchtigen Speicherzelle und dementsprechende Programmierungsschaltung
US6839284B1 (en) * 2003-06-17 2005-01-04 Powerchip Semiconductor Corp. Method of programming and erasing a non-volatile semiconductor memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000017357A (ko) * 1998-08-18 2000-03-25 가네꼬 히사시 반도체 기억 장치
JP2000188384A (ja) * 1998-12-22 2000-07-04 Toshiba Corp 不揮発性半導体記憶装置
US6188608B1 (en) * 1999-04-23 2001-02-13 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device
JP2001028196A (ja) * 1999-05-12 2001-01-30 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US6806525B2 (en) 2004-10-19
KR20030034016A (ko) 2003-05-01
US20050023601A1 (en) 2005-02-03
JP2003204001A (ja) 2003-07-18
US6927998B2 (en) 2005-08-09
JP4004809B2 (ja) 2007-11-07
US20030085421A1 (en) 2003-05-08

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