KR100512904B1 - 반도체소자의 제조방법 - Google Patents
반도체소자의 제조방법 Download PDFInfo
- Publication number
- KR100512904B1 KR100512904B1 KR10-1999-0061852A KR19990061852A KR100512904B1 KR 100512904 B1 KR100512904 B1 KR 100512904B1 KR 19990061852 A KR19990061852 A KR 19990061852A KR 100512904 B1 KR100512904 B1 KR 100512904B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- gas
- interlayer insulating
- etching process
- film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000007789 gas Substances 0.000 claims description 44
- 239000011229 interlayer Substances 0.000 claims description 33
- 239000010410 layer Substances 0.000 claims description 32
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- 230000005669 field effect Effects 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 238000001465 metallisation Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000002265 prevention Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000001721 carbon Chemical class 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (9)
- 반도체기판 상에 상측에 마스크절연막 패턴이 구비되고, 측벽에 절연막 스페이서가 구비되는 게이트전극과 소오스/드레인영역이 구비되는 모스전계효과 트랜지스터를 형성하는 공정과,반도체 소자의 비트라인콘택 및 저장전극 콘택으로 예정되는 부분에 접속되는 제1콘택플러그가 구비된 제1층간절연막을 형성하고, 전체표면 상부에 식각방지막을 형성하는 공정과,상기 제1콘택플러그에 접속된 제2콘택플러그 및 비트라인 구비된 제2층간절연막을 형성하는 공정과,상기 제2콘택플러그와 접속되는 캐패시터가 구비된 제3층간절연막을 형성하는 공정과,상기 제3층간절연막 상부에 금속배선콘택으로 예정되는 부분을 노출시키는 감광막 패턴을 형성하는 공정과,상기 식각방지막을 식각장벽으로 하여 제3층간절연막 및 제2층간절연막을 제거하는 제1단계식각공정과,상기 게이트전극 상의 식각방지막 및 마스크절연막 패턴과 반도체기판 상의 식각방지막과 소정 두께의 제1층간절연막을 제거하는 제2단계식각공정과,상기 반도체기판 상에 잔류하는 제1층간절연막을 제거하여 반도체기판을 노출시키는 제3단계식각공정과,상기 감광막 패턴을 제거하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 마스크절연막 패턴은 Si를 다량 함유하는 SiON막으로 형성되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 식각방지막은 SiN막 또는 SiON막을 형성되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제1층간절연막, 제2층간절연막 및 제3층간절연막은 상기 식각방지막과 식각선택비 차이를 갖는 산화막으로 형성되는 것을 특징으로 하는 반도체소자의 제조방법.
- 삭제
- 제 1 항에 있어서,상기 제1단계식각공정과 제3단계식각공정은 C2F6, C2F4, C3F6, C3F8, C4F6, C4F8, C5F8, C5F10 또는 C2HF5 등과 같이 다량의 폴리머를 유발하는 과탄소함유가스로 실시되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 6 항에 있어서,상기 제1단계식각공정과 제3단계식각공정은 상기 과탄소함유가스에 불활성가스를 혼합한 혼합가스가 식각가스로 사용되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제1단계식각공정과 제3단계식각공정은 상기 과탄소함유가스와 수소를 포함하는 가스의 혼합가스가 식각가스로 사용되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제2단계식각공정은 CF4, CHF3, NF3 또는 C2F6 등의 가스를 주식각가스로 하고, CH3F, CH2F2 또는 C2HF5 등의 가스를 혼합하거나, 불활성가스를 혼합하거나, 산소를 포함하는 가스를 혼합한 가스가 식각가스로 사용되는 것을 특징으로 하는 반도체소자의 제조방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1999-0061852A KR100512904B1 (ko) | 1999-12-24 | 1999-12-24 | 반도체소자의 제조방법 |
US09/745,429 US6660652B2 (en) | 1999-12-24 | 2000-12-26 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1999-0061852A KR100512904B1 (ko) | 1999-12-24 | 1999-12-24 | 반도체소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010063765A KR20010063765A (ko) | 2001-07-09 |
KR100512904B1 true KR100512904B1 (ko) | 2005-09-07 |
Family
ID=19629418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-1999-0061852A KR100512904B1 (ko) | 1999-12-24 | 1999-12-24 | 반도체소자의 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6660652B2 (ko) |
KR (1) | KR100512904B1 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100753097B1 (ko) * | 2002-06-29 | 2007-08-29 | 주식회사 하이닉스반도체 | 불화아르곤 노광원을 이용한 반도체소자 제조방법 |
KR100831978B1 (ko) * | 2002-07-19 | 2008-05-26 | 주식회사 하이닉스반도체 | 반사방지막을 이용한 비트라인콘택홀 형성 방법 |
KR100478498B1 (ko) * | 2003-01-30 | 2005-03-28 | 동부아남반도체 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
US7618898B2 (en) * | 2004-03-31 | 2009-11-17 | Nec Corporation | Method and apparatus for forming contact hole |
JP4761740B2 (ja) * | 2004-08-31 | 2011-08-31 | 東京エレクトロン株式会社 | マイクロレンズの形成方法 |
KR100744106B1 (ko) * | 2005-03-18 | 2007-08-01 | 주식회사 하이닉스반도체 | 더블 하드마스크를 구비하는 반도체소자 및 그의 제조 방법 |
US7351665B2 (en) * | 2005-03-28 | 2008-04-01 | Tokyo Electron Limited | Plasma etching method, plasma etching apparatus, control program, computer recording medium and recording medium having processing recipe recorded thereon |
KR100683492B1 (ko) * | 2005-12-28 | 2007-02-15 | 주식회사 하이닉스반도체 | 반도체소자의 콘택식각 방법 |
KR100744243B1 (ko) * | 2005-12-28 | 2007-07-30 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
KR101715861B1 (ko) * | 2010-12-02 | 2017-03-14 | 삼성전자주식회사 | 중수소 어닐링을 이용한 반도체 소자 형성방법 |
US20140074615A1 (en) * | 2012-09-10 | 2014-03-13 | Super Transcon Ip, Llc | Commerce System and Method of Controlling the Commerce System Using Triggered Advertisements |
CN107731739B (zh) * | 2016-08-12 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878642A (ja) * | 1994-09-06 | 1996-03-22 | Nippon Steel Corp | 半導体装置の製造方法 |
JPH09116013A (ja) * | 1995-10-24 | 1997-05-02 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
KR19990057892A (ko) * | 1997-12-30 | 1999-07-15 | 김영환 | 반도체 소자의 콘택 형성 방법 |
KR19990061053A (ko) * | 1997-12-31 | 1999-07-26 | 김영환 | 반도체 소자의 콘택홀 형성방법 |
KR19990085648A (ko) * | 1998-05-20 | 1999-12-15 | 윤종용 | 반도체소자의 콘택홀 형성방법 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5292677A (en) * | 1992-09-18 | 1994-03-08 | Micron Technology, Inc. | Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts |
GB2324408A (en) * | 1997-01-21 | 1998-10-21 | United Microelectronics Corporation | Forming DRAM cells |
-
1999
- 1999-12-24 KR KR10-1999-0061852A patent/KR100512904B1/ko active IP Right Grant
-
2000
- 2000-12-26 US US09/745,429 patent/US6660652B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878642A (ja) * | 1994-09-06 | 1996-03-22 | Nippon Steel Corp | 半導体装置の製造方法 |
JPH09116013A (ja) * | 1995-10-24 | 1997-05-02 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
KR19990057892A (ko) * | 1997-12-30 | 1999-07-15 | 김영환 | 반도체 소자의 콘택 형성 방법 |
KR19990061053A (ko) * | 1997-12-31 | 1999-07-26 | 김영환 | 반도체 소자의 콘택홀 형성방법 |
KR19990085648A (ko) * | 1998-05-20 | 1999-12-15 | 윤종용 | 반도체소자의 콘택홀 형성방법 |
Also Published As
Publication number | Publication date |
---|---|
US6660652B2 (en) | 2003-12-09 |
KR20010063765A (ko) | 2001-07-09 |
US20010005637A1 (en) | 2001-06-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6716766B2 (en) | Process variation resistant self aligned contact etch | |
KR100512904B1 (ko) | 반도체소자의 제조방법 | |
KR100376986B1 (ko) | 반도체소자의 제조방법 | |
KR100282416B1 (ko) | 반도체소자의제조방법 | |
KR100440076B1 (ko) | 반도체소자의 자기정렬적인 콘택 형성방법 | |
KR100440079B1 (ko) | 반도체소자의 자기정렬적인 콘택 형성방법 | |
KR20000045442A (ko) | 반도체소자의 콘택 형성방법 | |
KR100431818B1 (ko) | 반도체소자의 자기정렬적인 콘택 형성방법 | |
KR100835506B1 (ko) | 반도체소자의 제조방법 | |
KR100400321B1 (ko) | 반도체소자의 형성방법 | |
KR100372770B1 (ko) | 반도체소자의 자기정렬적인 콘택방법 | |
KR20070000719A (ko) | 반도체 소자의 비트라인콘택 형성방법 | |
KR100843903B1 (ko) | 반도체 소자의 제조방법 | |
KR100276562B1 (ko) | 반도체소자의콘택홀형성방법 | |
KR20030058634A (ko) | 반도체소자의 제조방법 | |
KR20030093715A (ko) | 반도체소자 제조 방법 | |
KR20010058545A (ko) | 반도체 소자 제조를 위한 자기정렬콘택 식각 방법 | |
KR20010004288A (ko) | 다단계 식각을 사용한 반도체 소자의 전도라인 형성방법 | |
KR100400298B1 (ko) | 반도체소자의 자기정렬적인 콘택방법 | |
KR100399935B1 (ko) | 반도체장치제조방법 | |
KR20050116665A (ko) | 반도체 소자의 형성 방법 | |
KR20010063777A (ko) | 반도체 소자의 제조 방법 | |
KR20010004378A (ko) | 반도체메모리소자 제조방법 | |
KR20040008467A (ko) | 반도체소자의 콘택홀 형성방법 | |
KR19990057377A (ko) | 반도체소자의 자기정렬적인 콘택방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120720 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20130723 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20140723 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20150721 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20160721 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20170724 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20180725 Year of fee payment: 14 |