KR100464563B1 - 반도체 패키지 및 그 제조방법 - Google Patents
반도체 패키지 및 그 제조방법 Download PDFInfo
- Publication number
- KR100464563B1 KR100464563B1 KR10-2000-0039957A KR20000039957A KR100464563B1 KR 100464563 B1 KR100464563 B1 KR 100464563B1 KR 20000039957 A KR20000039957 A KR 20000039957A KR 100464563 B1 KR100464563 B1 KR 100464563B1
- Authority
- KR
- South Korea
- Prior art keywords
- printed circuit
- circuit board
- semiconductor chip
- semiconductor package
- bump
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (11)
- 중앙이 개방된 형태의 인쇄회로기판과;상기 인쇄회로기판(32)의 중앙 개방부에 삽입 부착된 동일한 두께의 글래스(12)와;상기 인쇄회로기판(32)의 중앙 개방부 내주연으로 노출된 전도성패턴(15)에 범프(18)에 의하여 신호 교환 가능하게 융착된 반도체 칩(24)과;상기 범프(18)의 바깥쪽면를 따라 몰딩되어, 반도체 칩과 인쇄회로기판간의 접촉틈새를 마감하는 코팅재(20)와;상기 코팅재(20)가 내부로 범람되는 것을 방지할 수 있도록 상기 범프(18)의 안쪽을 따라 형성된 댐(22)과;상기 인쇄회로기판(32)상으로 비아홀을 통하여 노출된 전도성패턴(15)에 부착된 다수의 인출단자(26)로 구성된 것을 특징으로 하는 반도체 패키지.
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 중앙이 개방된 형태의 인쇄회로기판을 구비하여 제공하는 단계;상기 인쇄회로기판(32)의 중앙 개방부에 동일한 두께를 갖는 글래스(12)를 삽입 부착하는 단계;상기 인쇄회로기판(32)의 중앙 개방부 내주연으로 노출된 전도성패턴(15)과 반도체 칩의 본딩패드간을 범프(18)를 이용하여 신호 교환 가능하게 융착시키는 단계;상기 반도체 칩(24)의 사방 끝단부와 상기 인쇄회로기판간의 접촉 틈새를 가려주기 위하여 상기 범프(18)의 바깥쪽면을 따라 코팅재(20)를 몰딩하는 단계;상기 인쇄회로기판(32)상으로 비아홀을 통하여 노출된 전도성패턴(15)에 인출단자(26)를 부착시키는 단계로 이루어지는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 삭제
- 제 9 항에 있어서, 상기 코팅재(20)의 몰딩시, 코팅재(20)가 반도체 칩(24)의 안쪽으로 범람되는 것을 방지할 수 있도록 상기 범프(18)의 안쪽을 따라 댐(22)을 형성하는 단계가 더 진행되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0039957A KR100464563B1 (ko) | 2000-07-12 | 2000-07-12 | 반도체 패키지 및 그 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0039957A KR100464563B1 (ko) | 2000-07-12 | 2000-07-12 | 반도체 패키지 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020006343A KR20020006343A (ko) | 2002-01-19 |
KR100464563B1 true KR100464563B1 (ko) | 2004-12-31 |
Family
ID=19677643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2000-0039957A KR100464563B1 (ko) | 2000-07-12 | 2000-07-12 | 반도체 패키지 및 그 제조방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100464563B1 (ko) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020032027A (ko) * | 2000-10-25 | 2002-05-03 | 듀흐 마리 에스. | Ccd 이미징 칩용 패키징 구조 |
JP4505983B2 (ja) * | 2000-12-01 | 2010-07-21 | 日本電気株式会社 | 半導体装置 |
US6943423B2 (en) | 2003-10-01 | 2005-09-13 | Optopac, Inc. | Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof |
US6864116B1 (en) * | 2003-10-01 | 2005-03-08 | Optopac, Inc. | Electronic package of photo-sensing semiconductor devices, and the fabrication and assembly thereof |
US7122874B2 (en) * | 2004-04-12 | 2006-10-17 | Optopac, Inc. | Electronic package having a sealing structure on predetermined area, and the method thereof |
US6943424B1 (en) * | 2004-05-06 | 2005-09-13 | Optopac, Inc. | Electronic package having a patterned layer on backside of its substrate, and the fabrication thereof |
US20060043513A1 (en) * | 2004-09-02 | 2006-03-02 | Deok-Hoon Kim | Method of making camera module in wafer level |
KR100498708B1 (ko) | 2004-11-08 | 2005-07-01 | 옵토팩 주식회사 | 반도체 소자용 전자패키지 및 그 패키징 방법 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04137663A (ja) * | 1990-09-28 | 1992-05-12 | Toshiba Corp | 固体撮像装置 |
JPH08148526A (ja) * | 1994-09-22 | 1996-06-07 | Nec Corp | 半導体装置 |
JPH09330994A (ja) * | 1996-06-12 | 1997-12-22 | Texas Instr Japan Ltd | 半導体装置 |
JPH1065040A (ja) * | 1996-08-15 | 1998-03-06 | Nec Corp | 半導体装置 |
JPH10209322A (ja) * | 1997-01-22 | 1998-08-07 | Hitachi Ltd | 半導体装置およびその実装構造 |
JPH11176873A (ja) * | 1997-12-15 | 1999-07-02 | Hitachi Ltd | Bga形半導体装置およびその実装構造体 |
-
2000
- 2000-07-12 KR KR10-2000-0039957A patent/KR100464563B1/ko active IP Right Grant
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04137663A (ja) * | 1990-09-28 | 1992-05-12 | Toshiba Corp | 固体撮像装置 |
JPH08148526A (ja) * | 1994-09-22 | 1996-06-07 | Nec Corp | 半導体装置 |
JPH09330994A (ja) * | 1996-06-12 | 1997-12-22 | Texas Instr Japan Ltd | 半導体装置 |
JPH1065040A (ja) * | 1996-08-15 | 1998-03-06 | Nec Corp | 半導体装置 |
JPH10209322A (ja) * | 1997-01-22 | 1998-08-07 | Hitachi Ltd | 半導体装置およびその実装構造 |
JPH11176873A (ja) * | 1997-12-15 | 1999-07-02 | Hitachi Ltd | Bga形半導体装置およびその実装構造体 |
Also Published As
Publication number | Publication date |
---|---|
KR20020006343A (ko) | 2002-01-19 |
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