KR100426444B1 - Method for reducing coupling noise of semiconductor device - Google Patents

Abstract

PURPOSE: A method for reducing coupling noise of a semiconductor device is provided to intercept generation of coupling noise and contribute to operating stabilization of a semiconductor device by forming a ground voltage between silicon oxide layers for insulating conductive interconnections. CONSTITUTION: The first insulation layer(23) is formed on a predetermined underlying layer(21) during a process for fabricating a semiconductor device. The first and second conductive lines are formed on the first insulation layer. The second insulation layer(29) is deposited on the resultant structure. After a photoresist layer is formed on the second insulation layer, a photoresist layer pattern is formed to etch the insulation layer between the first and second conductive lines by a mask process. The second insulation layer under the photoresist layer pattern is etched by using the photoresist layer pattern as an etch barrier to form an opening between the first and second conductive lines. The photoresist layer pattern is eliminated. A conductive material is deposited on the resultant structure. The deposited conductive material is etched by an etch-back process to form the third conductive line in the opening. The third conductive line is formed between the first and second conductive lines. A ground voltage is applied to the third conductive line to remove the coupling noise.

Description

Coupling Noise Reduction Method of Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing coupling noise of semiconductor devices. In particular, in a high-speed integrated circuit device, a coupling is generated between the conductive wires by separating the conductive wires with ground power (Vss). A method for reducing coupling noise of a semiconductor device capable of reducing noise.

As semiconductor devices become more and more integrated, the distance between conductive wirings is reduced, and as the operation speed of the device increases, the influence of coupling noise generated between wirings increases.

In order to reduce the coupling noise phenomenon between the wirings, the silicon oxide film (SiO ₂ ) has been mainly used for the purpose of isolating the conductive wiring.

However, since the silicon oxide film has a large value of dielectric constant of about 3.9, coupling noise between wires is still generated, which may cause device malfunction.

FIG. 1 is a cross-sectional view showing two conductive lines insulated according to the related art, and a silicon oxide film 19 having a relatively high relative dielectric constant between two wires, that is, the conductive lines 15 and 17, as shown in the drawing. Insulated by).

In general, the coupling capacitance formed between the two wires 15 and 17 is proportional to the dielectric constant of the insulator that insulates the two conductive lines 11 and 13.

In particular, the influence of the coupling noise in the high-speed integrated circuit device is increasing, the main reason is as follows.

First, as the degree of integration of semiconductor devices increases, the load on a global bussing line such as a power line or an address line increases, so that the current flowing increases.

Second, the current increases as the operating speed of the semiconductor device increases.

Especially in the case of RAMBUS DRAMs whose operating speed reaches 600 MB / sec, the problem of coupling noise can be serious.

Therefore, in order to solve the above problems, the present invention is concerned with the fact that the electric field does not pass through the conductor, thereby preventing the occurrence of coupling noise by separating the ground noise between the silicon oxide films that insulate the conductive wires. It is an object of the present invention to provide a method of reducing coupling noise of a semiconductor device that may contribute to stabilization of operation.

1 is a cross-sectional view showing a state in which two conductive lines are insulated according to the related art.

2A-2E are cross-sectional views illustrating a process step of forming a third conductive line to reduce coupling noise generated between two conductive lines in accordance with the techniques of the present invention.

<Description of Symbols for Major Parts of Drawings>

11,21: lower layer 13,23: first insulating film

15,25: first conductive line 17,27: second conductive line

19,29: 2nd insulating film 31: Photosensitive film pattern

33: opening 35: third conductive material

37: third challenge line

According to the method of the present invention for achieving the above object,

Forming a first insulating film on a predetermined lower layer during a semiconductor device manufacturing process;

Forming a first conductive line and a second conductive line on the first insulating layer;

Depositing a second insulating film over the entire structure,

Forming a photoresist pattern for etching the insulating film between the first conductive line and the second conductive line by a mask process after coating the photoresist on the second insulating film;

Forming an opening between the first conductive line and the second conductive line by etching a lower second insulating layer using the photoresist pattern as an etch barrier;

Removing the photoresist pattern;

Depositing a conductive material over the entire structure, and

Etching the deposited conductive material by an etch back process to form a third conductive line in the opening;

The third conductive line is formed between the first and second conductive lines, and the ground voltage Vss is applied to the third conductive line to remove coupling noise.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating device manufacturing process steps in accordance with the method for reducing semiconductor device coupling noise of the present invention.

Referring to FIG. 2A, a first insulating layer 23 is formed on the lower layer 21, and a first conductive line 25 and a second conductive line 27 are formed on the first insulating layer 23. .

Next, in order to insulate the first conductive line 25 and the second conductive line 27, a second thickness 29 is deposited on the entire structure.

In this case, the second insulating layer 29 is typically formed of a silicon oxide film.

Referring to FIG. 2B, a photoresist is coated on the second insulating layer 29 and then a mask process is performed to etch the second insulating layer 29 between the first conductive line 25 and the second conductive line 27. The photosensitive film pattern 31 is formed.

Referring to FIG. 2C, the opening 33 is disposed between the first conductive line 25 and the second conductive line 27 by etching the lower second insulating layer 29 using the photoresist pattern 31 as a mask. Form.

In this case, the depth of the opening 33 formed between the first conductive line 25 and the second conductive line 27 may be formed to the lower end of each of the conductive lines 25 and 27 or to an intermediate region. have.

Referring to FIG. 2D, after removing the remaining photoresist pattern 31, the conductive material 35 is deposited on the entire structure.

Referring to FIG. 2E, the conductive material 35 is etched by an etch back process to etch the conductive material 35 only in the space 33 formed between the first conductive line 25 and the second conductive line 27. Is left to form the third conductive line 35.

Next, a ground voltage Vss (0V) is applied to the third conductive line 35 to separate the first conductive line 25 from the second conductive line 27.

Therefore, by applying VSS to the third conductive line 35 formed between the two conductive lines 25 and 27 as described above, coupling noise that may occur between the two conductive lines may be removed.

In addition, when the two conductive lines 25 and 27 are arranged up and down, the first conductive line 25 and the second conductive line 35 may be the same as the third conductive line 35 to which the Vss voltage is applied. 27) to reduce coupling noise.

As described above, taking into consideration that the electric field does not pass through the conductor, a third conductive line is formed between the silicon oxide films insulating the conductive wires, and the ground voltage is applied to the third conductive line. By applying the method of the present invention which reduces the coupling noise phenomenon generated between the conductive lines, in the high speed semiconductor integrated circuit device, malfunction of the device due to the coupling noise can be prevented. Since it does not need to be reworked, it can greatly contribute to shortening device development time, reducing design cost, and stabilizing device operation performance.

Claims (4)

Forming a first insulating film on a predetermined lower layer during a semiconductor device manufacturing process; Forming a first conductive line and a second conductive line on the first insulating layer; Depositing a second insulating film over the entire structure, Forming a photoresist pattern for etching the insulating film between the first conductive line and the second conductive line by a mask process after coating the photoresist on the second insulating film; Forming an opening between the first conductive line and the second conductive line by etching a lower second insulating layer using the photoresist pattern as an etch barrier; Removing the photoresist pattern; Depositing a conductive material over the entire structure, and Etching the deposited conductive material by an etch back process to form a third conductive line in the opening; Forming a third conductive line between the first and second conductive lines, and applying a ground voltage Vss to the third conductive line to remove coupling noise. The method of claim 1, wherein the first conductive line and the second conductive line are arranged vertically. The method of claim 1, wherein a depth of the opening formed between the first conductive line and the second conductive line is formed to a middle portion of the conductive line. The method of claim 1, wherein the first and second conductive lines are bit lines or word lines.