KR100191779B1 - Semiconductor device and its fabrication method - Google Patents

Abstract

According to the present invention, a semiconductor substrate is over-etched due to misalignment in a process of forming spacers using insulating films on both sidewalls of a device isolation region of a semiconductor device and forming a contact hole for contacting a capacitor lower electrode. A semiconductor device capable of preventing a well region from being short-circuited, wherein the semiconductor device includes a spacer formed on both sidewalls of the device isolation trench in a semiconductor device having a device isolation trench on a semiconductor substrate on which the well region is formed. And prevent electrical contact between the lower electrode of the capacitor formed on the semiconductor substrate and the well region. By such a method, it is possible to prevent the well region of the capacitor lower electrode and the semiconductor substrate from being shorted even when the semiconductor substrate is overetched in the process of forming a contact hole for the subsequent contact of the capacitor lower electrode. You can solve the problem.

Description

Trench for device isolation in semiconductor devices

1 is a cross-sectional view showing the structure of a conventional semiconductor device.

2 is an enlarged cross-sectional view for explaining a problem of a conventional semiconductor device.

3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

4A to 4C are sequential process diagrams showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: semiconductor substrate 12: device isolation region

11: first insulating film 11a: second insulating film

13: third insulating film 20: first interlayer insulating film

22: landing pad 24: second interlayer insulating film

26 bit line 28 third interlayer insulating film

30: polysilicon film for lower electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to forming a spacer using insulating films on both sidewalls of an isolation region of a semiconductor device, thereby forming a contact hole in which a capacitor lower electrode contacts. Therefore, the present invention relates to a semiconductor device capable of preventing a short circuit between a capacitor lower electrode and a well region of a semiconductor substrate even if the semiconductor substrate is overetched.

As the semiconductor devices are highly integrated, the size of the devices constituting the semiconductor device is also getting smaller, and accordingly, design rules for constituting the semiconductor devices are gradually decreasing.

As a result, it is difficult to perform a photolithography process for forming a contact hole to which a lower electrode and a bit line of a capacitor are connected in a memory cell region having a denser pattern than a peripheral circuit region of a semiconductor device. This follows.

1 illustrates a structure of a conventional semiconductor device in which a lower electrode and a bit line of a capacitor are formed.

Referring to FIG. 1, a conventional semiconductor device includes a semiconductor substrate 10 having a trench type isolation region 12 defining an active region and an inactive region of the semiconductor device, and on the semiconductor substrate 10 this technology. A gate electrode layer 16 formed using a technique well known in the art, a gate insulating layer 18 formed on the gate electrode layer 16, and a landing pad and a capacitor lower electrode on the gate insulating layer 18. On the land pad 22 and the landing pad 22 formed while filling the first interlayer insulating film 20 formed with holes, the contact holes in the region where the bit line of the semiconductor substrate 10 is formed. A second interlayer insulating film 24 formed to have a contact hole in which a bit line and a capacitor lower electrode contact each other, and a contact hole formed on the landing pad 22 among the contact holes, while filling the second interlayer insulating film 24. A bit line 26 formed thereon, A third interlayer insulating layer 28 formed on the second interlayer insulating layer 24 including a bit line 26 and having a contact hole in which a capacitor lower electrode is formed, and filling the contact hole while filling the contact hole. It has a structure including a capacitor lower electrode 30 formed on the interlayer insulating film 28.

However, in the conventional semiconductor device having the structure as described above, misalignment often occurs in the process of forming contact holes for contacting the capacitor lower electrode so that the semiconductor substrate is overetched as shown by reference numeral A in FIG. (over etched) problem is caused.

As a result, the capacitor lower electrode formed while filling the contact hole and the well region of the semiconductor substrate are short-circuited to increase the leakage current of the semiconductor device, resulting in a serious problem of malfunction of the semiconductor device.

An object of the present invention proposed to solve this problem is to form a spacer using an insulating film on both side walls of the device isolation region of the semiconductor device, so that the semiconductor substrate is overeated in the process of forming a contact hole to contact the lower electrode of the capacitor The present invention provides a semiconductor device capable of preventing a short circuit between a capacitor lower electrode and a semiconductor substrate from being shorted.

A semiconductor device of the present invention for achieving the object as described above, in the semiconductor device having a device isolation trench in a semiconductor substrate in which a well region is defined, comprising a dielectric insulating spacer formed on both side walls of the device isolation trench And prevent electrical contact between the lower electrode of the capacitor formed on the semiconductor substrate and the well region.

In a preferred embodiment of the present invention, the insulating film spacer is a silicon nitride film.

In a preferred embodiment of the present invention, the insulating film spacer is characterized in that it has a thickness range of about 500 ~ 1000Å.

By such a method, even when the semiconductor substrate is overetched in the process of forming a contact hole for contacting the capacitor lower electrode, the short region of the well region of the capacitor lower electrode and the semiconductor substrate can be prevented and the leakage current increases. The problem can be solved.

Best Mode for Carrying Out the Invention A preferred embodiment of the present invention will be described in detail with reference to FIG. 3 and FIG. 4A to FIG. 4C.

Referring to FIG. 3, in the semiconductor device according to the preferred embodiment of the present invention, the semiconductor substrate 10 is etched to form a trench, and device isolation having spacers 13a using insulating films on both side walls thereof. A region 12, a gate electrode layer 16 formed on the semiconductor substrate 10, a gate insulating film 18 formed on the gate electrode layer 16, a landing pad and a capacitor on the gate insulating film 18 A first interlayer insulating film 20 formed to have a contact hole for contacting the lower electrode, a landing pad 22 formed while filling a contact hole in a region in which a bit line of the semiconductor substrate 10 is formed among the contact holes; While filling the second interlayer insulating film 24 formed to have a contact hole for contacting the bit line and the capacitor lower electrode on the landing pad 22, and the contact hole formed on the land pad 22 of the contact hole The second interlayer insulating film 24 A third interlayer insulating film 28 formed on the second interlayer insulating film 24 including the bit line 26 formed on the second interlayer insulating film 24, wherein the lower capacitor layer is formed to have a contact hole; And a capacitor lower electrode 30 formed on the third interlayer insulating layer 28 while filling the contact hole.

By the device isolation trench of the semiconductor device, the short region between the capacitor lower electrode and the semiconductor substrate can be prevented from being shorted, and the problem of increased leakage current can be solved.

In FIG. 3 and FIGS. 4A to 4C, the same reference numerals are given to the same components having the same functions as those of the semiconductor device shown in FIG.

3 shows the structure of a semiconductor device according to a preferred embodiment of the present invention.

The semiconductor device having the structure as described above is manufactured by the following method.

4A to 4C sequentially illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, a first insulating film and a second insulating film are sequentially formed on the semiconductor substrate 10 on which the well region 10a is defined, thereby defining the device isolation region of the semiconductor substrate 10. When the second insulating layer is patterned, a second insulating layer pattern 11a used as a mask is formed in a subsequent etching process.

Subsequently, using the second insulating layer pattern 11a as a mask, the first insulating layer and the semiconductor substrate 10 are sequentially etched to a predetermined thickness to form the trench 12 for device isolation, and then the etching process. Compensation for both side walls of the device isolation trench 12 damaged by the oxidative cavity. The third insulating layer 13 is formed on the second insulating layer pattern 11a including the device isolation trench 12.

Next, when the third insulating film 13 is etched by an etch back process, an insulating film spacer 13a is formed on both sidewalls of the device isolation trench 12 as shown in FIG. 4B, and then the device isolation is performed. The oxide film 14 is filled in the trench 12.

Then, the first and second insulating films 11 and 11a on the semiconductor substrate 10 are sequentially removed, and then, on the semiconductor substrate 10, a technique well known in the art is shown in FIG. 4B. As shown, the gate electrode 16 and the gate insulating film 18 are formed.

Finally, referring to FIG. 4C, a first interlayer insulating film 20 having a contact hole for connecting the landing pad 22 to the semiconductor substrate 10 is formed, and the gate is filled with the contact hole. A landing pad 22 is formed on the insulating film 18 to contact the bit lines.

Subsequently, after forming the second interlayer insulating layer 24 including the landing pad 22 and having a contact hole in which a bit line is formed on the first interlayer insulating layer 20, the landing pad 22 is formed on the landing pad 22. The bit line 26 is formed on the second interlayer insulating layer 24 while filling the formed contact hole.

Next, a third interlayer insulating film 28 is formed on the second interlayer insulating film 24 including the bit line 26. In addition, the contact region of the capacitor lower electrode of the semiconductor substrate 10 is defined to form the third interlayer insulating film 28, the second interlayer insulating film 24, the first interlayer insulating film 20, the gate insulating film 18, and the like. After etching sequentially to form a contact hole, the polysilicon 30 for the capacitor lower electrode 30 is formed on the third interlayer insulating film 30 while filling the contact hole.

According to the conventional method of manufacturing a semiconductor device, misalignment often occurs in a process of forming a contact hole for contacting a capacitor lower electrode of the semiconductor device. As a result, as shown in FIG. The problem of over etching has occurred.

As a result, in the conventional semiconductor device, the capacitor lower electrode formed while filling the contact hole and the well region of the semiconductor substrate are short-circuited to increase the leakage current of the semiconductor device, which in turn causes a serious problem of a malfunction of the semiconductor device.

In order to solve this problem, the present invention proposes to form a trench type device isolation region by etching a semiconductor substrate using a technique well known in the art, and then forming insulating film spacers on both side walls of the device isolation region. An oxide film is filled in the device isolation region to form a trench type device isolation region.

Therefore, even when the semiconductor substrate is overetched in the process of forming a contact hole in which the capacitor lower electrode contacts, the insulating layer spacers formed on both side walls of the device isolation region play a blocking role. It is possible to prevent the well region from being short-circuited and to solve the problem of an increase in leakage current.

Claims (2)

A semiconductor device having a trench 12 for device isolation in a semiconductor substrate 10 having a well 10a formed therein, wherein the silicon nitride film spacers 13a formed on both sidewalls of the device isolation trench 12 are provided. A trench for device isolation in a semiconductor device, characterized in that it has a structure that prevents electrical contact between the lower electrode (30) of the capacitor formed on the semiconductor substrate (10) and the well (10a). The trench of claim 1, wherein the silicon nitride film spacer has a thickness in a range of about 500 kV to about 1000 kPa.