KR100389019B1 - Reset Circuit in Plasma Display Panel - Google Patents

Abstract

The present invention relates to a reset circuit of a plasma display panel that can stabilize a driving operation at power on / off.

The reset circuit of the plasma display panel has a plurality of output lines and a plurality of power supply terminals, a power supply for generating driving power required for the plasma display panel through the output line and generating on / off voltage through the power supply terminal. And a plurality of capacitors connected to each of the output lines of the power supply, and a plurality of capacitors for discharging the voltage of the capacitor in response to an on / off voltage connected between the power supply terminal and the capacitor and input from the power supply terminal. A reset part is provided. Each of the reset units may independently discharge the voltage of the capacitor.

By such a configuration, the reset circuit of the plasma display panel according to the present invention can stabilize the driving operation and prevent destruction of the driving element.

Description

Reset Circuit in Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a reset circuit of a plasma display panel capable of stabilizing a driving operation at power on / off.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when ultraviolet light generated by gas discharge excites the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge PDP.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 12Y and the common sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

2 is a view showing a driving apparatus of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 2, in the conventional three-electrode alternating current surface-discharge type PDP driving apparatus, m × n discharge cells 1 have scan / sustain electrode lines Y1 to Ym and common sustain electrode lines Z1 to Zm. ) And a PDP 30 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 32 for driving the scan / sustain electrode lines Y1 to Ym; Common sustain driver 34 for driving common sustain electrode lines Z1 to Zm, odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and even-numbered address electrode lines First and second address drivers 36A and 36B for dividing and driving (X2, X4, ..., Xn-2, Xn) are provided. The scan / sustain driver 32 sequentially supplies scan pulses and sustain pulses to the scan / sustain electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × n The discharge in each of the four discharge cells 1 is continued. The common sustain driver 34 supplies a sustain pulse to all of the common sustain electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supply image data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, and the second address driver 36B supplies the even-numbered address electrode lines ( Image data is supplied to X2, X4, ..., Xn-2, Xn).

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different discharge times in order to express gray levels of an image. Each subfield is further divided into a reset period for uniformly discharging the discharge, an address period for selecting the discharge cells, and a sustain period for expressing the gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. In addition, each of the eight subfields SF1 to SF8 is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased.

4 is a waveform diagram showing a driving waveform supplied to each electrode line of the PDP in each subfield in the conventional method of driving a three-electrode AC surface discharge type PDP.

Referring to FIG. 4, one subfield is divided into a reset period for initializing the entire screen, an address period for writing data while scanning the entire screen in a linear sequential manner, and a sustain period for maintaining the light emission state of the cells in which the data is written. Lose. First, during the reset period, the discharge cells are initialized, and discharge is generated between the scan / sustain electrode line (Y) and the common sustain electrode line (Z) by a discharge pulse supplied to the common sustain electrode line (Z) to assist the address discharge. Priming charged particles and wall charges are formed in the cells. In the address period, scan pulses (-Vs) are sequentially applied to each scan / sustain electrode line (Y) of the PDP, and data pulses (Vd) are supplied to each address electrode line (X) in synchronization with the scan pulses. At this time, a common level DC voltage is supplied to the common sustain electrode lines Z, and the DC voltage enables stable address discharge between the address electrode line X and the scan / sustain electrode line Y. . In the sustain period, a sustain pulse is supplied to the scan / sustain electrode line Y and the common sustain electrode line Z to emit light of the selected discharge cells in the address period.

As such, the reset pulse Vsetup, the scan pulse Vscan, and the sustain pulse Vsus input to the scan / sustain driver 32 or the common sustain driver 34 to drive the PDP are as shown in FIG. 5. Generated at power supply 40 (hereinafter referred to as "PS"). The scan pulses Vscan and the sustain pulses Vsus generated by the PS 40 are input to the scan / sustain driver 32 and alternately generated with the sustain pulses Vsus input to the scan / sustain driver 32. The sustain pulse Vsus and the reset pulse Vsetup are input to the common sustain driver 34. Lines 41, 42, for transferring the reset pulse Vsetup, scan pulse Vscan, and sustain pulse Vsus generated from the PS 40 to the scan / sustain driver 32 or the common sustain driver 34. Capacitors C1, C2, C3 are connected to 43. The capacitors C1, C2, and C3 have a large capacitance value of about 300 mA to 500 mA and stabilize the voltages on the lines 41, 42, and 43.

However, in the conventional PDP, the capacitors C1, C2, and C3 have a residual voltage even when the PDP is turned off. That is, the capacitors C1, C2, and C3 having a large capacitance value do not discharge in a short time when the PDP is powered off, and have a certain residual voltage. If the power of the PDP is turned on in the state where the residual voltage exists in the capacitors C1, C2, and C3, the driving operation of the PDP becomes unstable, and the driving device may be destroyed.

Accordingly, an object of the present invention is to provide a reset circuit of a plasma display panel which can stabilize the driving operation at the time of power supply on / off.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode PDP.

FIG. 2 is a plan view showing an arrangement of electrode lines and discharge cells of the PDP shown in FIG. 1; FIG.

3 is a diagram illustrating gray levels of one frame in the PDP shown in FIG. 1;

FIG. 4 is a waveform diagram showing driving waveforms supplied to respective electrode lines of the plasma display panel for each subfield in the PDP driving method shown in FIG. 1;

FIG. 5 is a diagram of a power supply generating the drive waveform shown in FIG. 4; FIG.

6 is a block diagram showing a driving waveform supply unit according to an embodiment of the present invention.

7 is a circuit diagram showing in detail the reset unit shown in FIG.

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12Y: scan / sustain electrode 12Z: common sustain electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X: address electrode

24: partition 26: phosphor layer

30: PDP 32: scan / sustain drive unit

34: common sustain driver 36A, 36B: address driver

40: power supply 41,42,43: line

44, 46, 48: reset section 50: transistor

52: node point

In order to achieve the above object, the reset circuit of the plasma display panel of the present invention has a plurality of output lines and a plurality of power terminals to generate the driving power required for the plasma display panel through the output line and also through the power terminal. A power supply generating an on / off voltage, capacitors connected to each of the output lines of the power supply, and in response to an on / off voltage connected between the power supply terminal and the capacitor and input from the power supply terminal; A plurality of reset parts for discharging the voltage of the capacitor are provided. Each of the reset units may independently discharge the voltage of the capacitor.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 7.

6 is a view showing a drive waveform supply unit according to an embodiment of the present invention.

Referring to FIG. 6, a driving waveform supply unit according to an embodiment of the present invention generates a reset pulse Vsetup, a scan pulse Vscan, and a sustain pulse Vsus to supply the scan / sustain driver or the common sustain driver. 40, the lines 41, 42 and 43 provided between the PS 40 and the scan / sustain driver or the common sustain driver, and the residual voltages present on the lines 41, 42 and 43. Reset parts 44, 46, and 48 for forcibly discharging are provided. Capacitors C1, C2, C3 are connected to lines 41, 42, 43, and these capacitors C1, C2, C3 stabilize the voltage on lines 41, 42, 43. The reset parts 44, 46, and 48 are present in the capacitors C1, C2, and C3 by connecting the capacitors C1, C2, and C3 to the ground voltage source GND when the power of the PDP is turned off. Discharge the residual voltage.

7 is a circuit diagram illustrating in detail the reset units of the present invention.

Referring to FIG. 7, the reset parts 44, 46, and 48 of the present invention may be connected to a transistor 50, an emitter of the transistor 50, and the lines 41, 42, and 43. The first resistor R1 and the second resistor R2 are connected between the base of the transistor 50 and the voltage source Vc, and are connected between the second resistor R2 and the base voltage source GND. And a third resistor R3. The collector of the transistor 50 is connected to the ground voltage source GND. The voltage source Vc receives a voltage of +5 V from the PS 40 and supplies it to the second and third resistors R2 and R3.

In detail, first, when the power of the PDP is turned on, a voltage of +5 V is applied to the second and third resistors R2 and R3 from the PS 40. When a voltage of +5 V is applied to the second and third resistors R2 and R3, a predetermined voltage is applied to the node point 52 between the second and third resistors R2 and R3. At this time, if the second and third resistors R2 and R3 have the same resistance value, a voltage of 2.5V is applied to the node point 52. The predetermined voltage applied to the node point 52 is applied to the base of the transistor 50, so that the transistor 50 is turned off. When the transistor 50 is turned off, the reset pulse (Vsetup), the scan pulse (Vscan) and the sustain pulse (from the PS 40 to the scan / sustain driver or the common sustain driver via the lines 41, 42, and 43) Vsus) is supplied. That is, the PDP will operate normally.

When the power of the PDP is turned off, a voltage of 0 V is applied to the second and third resistors R2 and R3 from the PS 40. When a voltage of 0 V is applied to the second and third resistors R2 and R3, a voltage of 0 V is also applied to the node point 52 between the second and third resistors R2 and R3. When a voltage of 0 V is applied to the node point 52, the transistor 50 is turned on. When the transistor 50 is turned on, the capacitors C1, C2, and C3 connected to the lines 41, 42, and 43 are connected to the ground voltage source GND. When the capacitors C1, C2 and C3 and the ground voltage source GND are connected, the residual voltages of the capacitors C1, C2 and C3 are discharged.

As described above, according to the reset circuit of the plasma display panel according to the present invention, when the plasma display panel is turned off, the capacitors are connected to the base voltage source to discharge the residual voltage of the capacitor. Therefore, it is possible to stabilize the driving operation at the time of power supply on / off and to prevent the destruction of the driving element.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

A power supply having a plurality of output lines and a plurality of power terminals and generating driving power required for a plasma display panel through the output lines, and generating an on / off voltage through the power terminals; Capacitors connected to each of the output lines of the power supply; A plurality of reset parts connected between the power supply terminal and the capacitor and configured to discharge the voltage of the capacitor in response to an on / off voltage input from the power supply terminal, And each of the reset units independently discharges the voltage of the capacitor . delete The method of claim 1, The reset unit, Transistors, A first resistor disposed between the emitter of the transistor and the output line of the power supply; A second resistor connected between the base of the transistor and a power supply terminal of the power supply; And a third resistor connected between the base of the transistor and a base voltage source. The method of claim 3, wherein And the collector of the transistor is connected to the base voltage source. delete delete