JPH07210112A - Residual charge discharging circuit - Google Patents
Residual charge discharging circuitInfo
- Publication number
- JPH07210112A JPH07210112A JP6001877A JP187794A JPH07210112A JP H07210112 A JPH07210112 A JP H07210112A JP 6001877 A JP6001877 A JP 6001877A JP 187794 A JP187794 A JP 187794A JP H07210112 A JPH07210112 A JP H07210112A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- resistor
- power source
- turned
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of Gas Discharge Display Tubes (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は残留電荷放電回路に係
り、PDP(プラズマディスプレイパネル)を用いた装
置の電源オフ時、電源の平滑コンデンサの残留電荷を短
時間で放電させるものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a residual charge discharging circuit, and more particularly to a residual charge discharging circuit for discharging residual charge of a smoothing capacitor of a power source in a short time when the power source of a device using a PDP (plasma display panel) is turned off.
【0002】[0002]
【従来の技術】PDPはセルの放電で発光するもので、
この放電のためのパルス状の電流がPDPに流入する
が、電流は、例えば、約5マイクロ秒の間に最大数アン
ペアもの電流が流れる。このため、PDPの電源回路の
平滑用コンデンサには大容量のものを使用し、短時間に
大電流を供給できるようにしている。ところで、PDP
は、装置の構成上の必要性から装置本体と切離せるよう
にするため、着脱自在なコネクタを用いて接続線により
電源回路とPDP回路とを接続しているものがある。そ
して、PDPを取り外す場合、電源スイッチをオフして
からコネクタを抜去するのであるが、PDPは突入電流
によって破壊され易いものであり、しかも、上述の如く
電源回路には大容量の平滑コンデンサが用いられるた
め、電源オフからコネクタを抜去するまでの操作が短時
間のうちに行われた場合、平滑コンデンサに蓄積された
電荷が放電し終わらないうちにコネクタが抜去されるこ
とになり、この抜去の際にコネクタ・ソケットの接点間
で接/断が繰り返されたり、あるいは抜去後すぐに再接
続したような場合、平滑コンデンサの残留電荷がPDP
に突入し、PDPが破壊されるという問題が発生する。2. Description of the Related Art A PDP emits light by discharging a cell.
A pulsed current for this discharge flows into the PDP, and as the current, for example, a current of up to several amperes flows in about 5 microseconds. For this reason, a large-capacity smoothing capacitor is used for the power supply circuit of the PDP so that a large current can be supplied in a short time. By the way, PDP
In some cases, a power supply circuit and a PDP circuit are connected to each other by a connecting line using a detachable connector in order to be separated from the main body of the apparatus due to the necessity of the configuration of the apparatus. When removing the PDP, the power switch is turned off and then the connector is pulled out. However, the PDP is easily destroyed by the inrush current. Moreover, as described above, a large-capacity smoothing capacitor is used in the power circuit. Therefore, if the operation from turning off the power to removing the connector is performed in a short time, the connector will be removed before the charge accumulated in the smoothing capacitor is completely discharged. In this case, if the contact / disconnection between the contacts of the connector / socket is repeated, or if it is reconnected immediately after the removal, the residual charge of the smoothing capacitor is
However, there is a problem that the PDP is destroyed and the PDP is destroyed.
【0003】[0003]
【発明が解決しようとする課題】本発明はこのような点
に鑑み、電源をオフしたとき、電源の平滑コンデンサの
残留電荷を迅速に放電させ、電源オフ後であれば、電源
供給配線のコネクタを挿抜してもPDPに電流が突入し
ないようにしてPDPの破壊を防止するものを提供する
ことにある。SUMMARY OF THE INVENTION In view of the above problems, the present invention quickly discharges the residual charge of the smoothing capacitor of the power source when the power source is turned off, and the connector of the power supply wiring after the power source is turned off. An object of the present invention is to provide a device that prevents current from entering the PDP even when the PDP is inserted or removed to prevent the PDP from being destroyed.
【0004】[0004]
【課題を解決するための手段】本発明は上述の課題を解
決するため、コンデンサで平滑した直流電源を供給する
第1電源と、前記第1電源より着脱可能な接続線により
電源供給を受ける負荷回路とでなるものにおいて、前記
第1電源の電圧よりも低い直流電圧で、電源オフにて電
圧が急速に降下する第2電源に第1抵抗器を介してベー
ス電極を接続し、前記第1電源および接地間に直列接続
した第2抵抗器および第3抵抗器の接続点にエミッタ電
極を接続し、コレクタ電極を第4抵抗器を介して接地し
たPNP型トランジスタと、前記第1電源にアノード電
極を接続し、カソード電極を接地し、前記PNP型トラ
ンジスタのコレクタ電極にゲート電極を接続したサイリ
スタとでなり、前記第2抵抗器および第3抵抗器によ
り、電源オン時には前記PNP型トランジスタを非導通
にする電圧をエミッタ電極に印加するようにして構成し
た残留電荷放電回路を提供するものである。In order to solve the above-mentioned problems, the present invention solves the above-mentioned problems by providing a first power source for supplying a DC power source smoothed by a capacitor and a load which is supplied with power from a connection line detachable from the first power source. A circuit comprising a base electrode connected via a first resistor to a second power supply whose DC voltage is lower than the voltage of the first power supply and whose voltage rapidly drops when the power is off. A PNP transistor having an emitter electrode connected to a connection point of a second resistor and a third resistor connected in series between a power supply and ground, and a collector electrode grounded via a fourth resistor; and an anode connected to the first power supply. A thyristor in which an electrode is connected, a cathode electrode is grounded, and a gate electrode is connected to a collector electrode of the PNP type transistor. When the power is turned on, the thyristor includes a second resistor and a third resistor. The voltage of the serial PNP transistor nonconductive and provides a residual charge discharging circuit which is to configured to be applied to the emitter electrode.
【0005】[0005]
【作用】以上のように構成したので、本発明による残留
電荷放電回路においては、PNP型トランジスタのベー
スは、電源オフにて電圧が急速に降下する電源に接続さ
れているが、エミッタを接続しているPDP電源の電圧
は降下速度が遅く、このため、電源オフにてトランジス
タのベース電圧が降下し、ベース・エミッタ間が順バイ
アスされてトランジスタはオン状態となり、コレクタの
電圧が上昇する。これにより、コレクタに接続されてい
るサイリスタのゲートの電圧が上昇し、サイリスタが導
通し、アノード・カソード間がオン状態になり、アノー
ドに接続されているPDP電源の残留電荷はサイリスタ
を介して放電する。With the above construction, in the residual charge discharging circuit according to the present invention, the base of the PNP transistor is connected to the power supply whose voltage drops rapidly when the power is turned off, but the emitter is connected. The voltage of the PDP power supply is slow to drop. Therefore, when the power is turned off, the base voltage of the transistor drops, the base-emitter is forward biased, the transistor is turned on, and the collector voltage rises. As a result, the voltage of the gate of the thyristor connected to the collector rises, the thyristor becomes conductive, the anode-cathode is turned on, and the residual charge of the PDP power supply connected to the anode is discharged through the thyristor. To do.
【0006】[0006]
【実施例】以下、図面に基づいて本発明による残留電荷
放電回路の実施例を詳細に説明する。図1は本発明によ
る残留電荷放電回路の一実施例の要部回路接続図であ
る。図において、1はトランスで、例えば、スイッチン
グ式電源の変圧トランスである。2はダイオードで、ト
ランス1のLow-B用巻線出力を整流しLow-B電圧(A
点、例えば、5ボルト)を出力する。3は平滑コンデン
サであるが、小容量のもので、電源オフにて電荷は急速
に放電される。4はダイオードで、トランス1のHigh−
B用巻線出力を整流しHigh−B電圧(B点、例えば、20
0 ボルト)を出力する。5は平滑コンデンサで、短時間
に大電流が流れるPDP等の負荷回路に充分な電流を供
給できるようにするため大容量のものを使用する。Embodiments of the residual charge discharging circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit connection diagram of essential parts of an embodiment of a residual charge discharging circuit according to the present invention. In the figure, 1 is a transformer, for example, a transformer of a switching power supply. Reference numeral 2 is a diode, which rectifies the output of the winding for Low-B of the transformer 1 and outputs Low-B voltage (A
Point, for example 5 volts). Reference numeral 3 denotes a smoothing capacitor, which has a small capacity and whose electric charge is rapidly discharged when the power is turned off. 4 is a diode, High- of the transformer 1
High-B voltage (B point, for example, 20
Output 0 volt). A smoothing capacitor 5 has a large capacity and is used in order to supply a sufficient current to a load circuit such as a PDP in which a large current flows in a short time.
【0007】6はPNP型のトランジスタで、ベースに
抵抗器7を介してLow-B(A点)電圧を印加し(抵抗器
8≫抵抗器7に設定し、ベースに略A点電圧が印加され
るようにする)、エミッタを、High−B(B点)〜接地
間に直列接続した抵抗器9および抵抗器10によるHigh−
B電圧の分圧点に接続し、コレクタを、ダイオード11お
よび抵抗器12を介して接地する。13はコンデンサであ
る。14はサイリスタで、アノードをHigh−Bに接続し、
カソードを抵抗器15を介して接地し、ゲートを前記ダイ
オード11および抵抗器12の接続点に接続する。Reference numeral 6 is a PNP type transistor, which applies a Low-B (point A) voltage to the base through a resistor 7 (resistor 8 >> resistor 7 is set, and a voltage of approximately point A is applied to the base). High-B by the resistor 9 and the resistor 10 in which the emitter is connected in series between High-B (point B) and the ground.
It is connected to the voltage divider of the B voltage and the collector is grounded via diode 11 and resistor 12. 13 is a capacitor. 14 is a thyristor, the anode of which is connected to High-B,
The cathode is grounded via a resistor 15, and the gate is connected to the connection point of the diode 11 and the resistor 12.
【0008】電源がオンされているとき、トランジスタ
6のベース電圧は略Low-B電圧である。トランジスタ6
のエミッタには、High−B電圧を抵抗器9と抵抗器10で
分圧した電圧が印加されているが、このエミッタ電圧が
トランジスタ6がオンしない電圧になるように抵抗器9
と抵抗器10の値を設定し、かつ、Low-B電圧が降下して
トランジスタ6がオンしたとき、ダイオード11と抵抗器
12の接続点の電圧がサイリスタ13をオンにするゲート電
圧になるように、エミッタ側の抵抗器9およびコレクタ
側の抵抗器12の値をそれぞれ設定する。ダイオード11お
よびコンデンサ13は、トランジスタ6のオンにより抵抗
器12の両端に生じた電圧(サイリスタ14のゲート電圧)
が、トランジスタ6がオフした後も暫く保持されるよう
にする。抵抗器15は、サイリスタ14の電流値が許容電流
値以内になるように設定する。When the power supply is turned on, the base voltage of the transistor 6 is approximately a Low-B voltage. Transistor 6
A voltage obtained by dividing the High-B voltage by the resistors 9 and 10 is applied to the emitter of the resistor 9. The resistor 9 is set so that the emitter voltage becomes a voltage at which the transistor 6 does not turn on.
And the value of the resistor 10 are set, and when the Low-B voltage drops to turn on the transistor 6, the diode 11 and the resistor 10
The values of the resistor 9 on the emitter side and the resistor 12 on the collector side are set so that the voltage at the connection point of 12 becomes the gate voltage for turning on the thyristor 13. The diode 11 and the capacitor 13 generate a voltage across the resistor 12 when the transistor 6 is turned on (gate voltage of the thyristor 14).
However, it is held for a while even after the transistor 6 is turned off. The resistor 15 is set so that the current value of the thyristor 14 is within the allowable current value.
【0009】以上の回路設定により、コンデンサ5が大
容量のため、電源オフ時、PDPの電源のB点の電圧
(High−B)は、図2に示す一例のように電圧の降下速
度が遅く、トランジスタ6のエミッタ電圧も緩やかに降
下する。ところが、A点の電圧(Low-B)は電源オフに
て急速に降下し、トランジスタ6のベース電圧も急速に
降下し、エミッタ・ベース間に順バイアスがかかる。こ
れにより、トランジスタ6はオン状態になり、コレクタ
電圧が、略、B点電圧を抵抗器9と抵抗器12との比で分
割した電圧になる。これにより、サイリスタ14がオン
し、コンデンサ5に残留していた電荷がサイリスタ14お
よび抵抗器15を経て放電される。この放電は、B点の電
圧が降下してトランジスタ6のエミッタ電圧が所要の電
圧、すなわちLow-B電圧+α(トランジスタ6のベース
電圧にバイアス電圧を加えた値)以下になり、コンデン
サ13の電荷が放電してサイリスタ14がオンできなくなる
まで継続する。With the above circuit settings, since the capacitor 5 has a large capacity, the voltage (High-B) at the point B of the power source of the PDP has a slow voltage drop rate when the power is off, as in the example shown in FIG. , The emitter voltage of the transistor 6 also drops gently. However, the voltage at point A (Low-B) drops rapidly when the power is turned off, the base voltage of the transistor 6 also drops rapidly, and forward bias is applied between the emitter and the base. As a result, the transistor 6 is turned on, and the collector voltage becomes substantially the voltage obtained by dividing the B point voltage by the ratio of the resistor 9 and the resistor 12. As a result, the thyristor 14 is turned on, and the electric charge remaining in the capacitor 5 is discharged through the thyristor 14 and the resistor 15. In this discharge, the voltage at the point B drops, the emitter voltage of the transistor 6 becomes the required voltage, that is, the Low-B voltage + α (value obtained by adding the bias voltage to the base voltage of the transistor 6) or less, and the charge of the capacitor 13 is reduced. Will be discharged until thyristor 14 can no longer be turned on.
【0010】[0010]
【発明の効果】以上に説明したように、本発明による残
留電圧放電回路によれば、電源オフにより、PDPの電
源の平滑コンデンサの残留電荷はサイリスタを介して急
速に放電されるので、PDPの電源供給配線のコネクタ
を挿抜してもPDPを破壊する電流の突入があり得ず、
PDPと電源とを接続するコネクタを安易に着脱できる
ので作業能率が向上する。As described above, according to the residual voltage discharging circuit of the present invention, when the power supply is turned off, the residual charge of the smoothing capacitor of the power supply of the PDP is rapidly discharged through the thyristor. Even if the connector of the power supply wiring is inserted or removed, there is no inrush of current that destroys the PDP.
Since the connector for connecting the PDP and the power source can be easily attached and detached, work efficiency is improved.
【図1】本発明による残留電圧放電回路の一実施例の要
部回路接続図である。FIG. 1 is a circuit diagram of a main part of an embodiment of a residual voltage discharge circuit according to the present invention.
【図2】本発明による残留電圧放電回路の動作を説明す
るための電源オフ時の電圧変化を示す図である。FIG. 2 is a diagram showing a voltage change when the power is turned off for explaining the operation of the residual voltage discharge circuit according to the present invention.
1 トランス 2 ダイオード 3 平滑コンデンサ 4 ダイオード 5 平滑コンデンサ 6 PNP型トランジスタ 7 抵抗器 9 抵抗器 10 抵抗器 11 ダイオード 12 抵抗器 13 コンデンサ 14 サイリスタ 1 Transformer 2 Diode 3 Smoothing Capacitor 4 Diode 5 Smoothing Capacitor 6 PNP Transistor 7 Resistor 9 Resistor 10 Resistor 11 Diode 12 Resistor 13 Capacitor 14 Thyristor
Claims (2)
る第1電源と、前記第1電源より着脱可能な接続線によ
り電源供給を受ける負荷回路とでなるものにおいて、前
記第1電源の電圧よりも低い直流電圧で、電源オフにて
電圧が急速に降下する第2電源に第1抵抗器を介してベ
ース電極を接続し、前記第1電源および接地間に直列接
続した第2抵抗器および第3抵抗器の接続点にエミッタ
電極を接続し、コレクタ電極を第4抵抗器を介して接地
したPNP型トランジスタと、前記第1電源にアノード
電極を接続し、カソード電極を接地し、前記PNP型ト
ランジスタのコレクタ電極にゲート電極を接続したサイ
リスタとでなり、前記第2抵抗器および第3抵抗器によ
り、電源オン時には前記PNP型トランジスタを非導通
にする電圧をエミッタ電極に印加するようにして構成し
た残留電荷放電回路。1. A first power source for supplying a DC power source smoothed by a capacitor, and a load circuit for receiving power from a connection line detachable from the first power source, the voltage of which is higher than the voltage of the first power source. A base electrode is connected via a first resistor to a second power source whose voltage drops rapidly when the power source is turned off at a low DC voltage, and a second resistor and a third resistor connected in series between the first power source and ground. A PNP type transistor in which an emitter electrode is connected to a connection point of a resistor and a collector electrode is grounded through a fourth resistor, and an anode electrode is connected to the first power source and a cathode electrode is grounded, and the PNP type transistor is connected. And a thyristor having a gate electrode connected to the collector electrode thereof, the second resistor and the third resistor are used to generate a voltage for turning off the PNP transistor when the power is turned on. A residual charge discharge circuit configured to be applied to the electrode.
極および第4抵抗器の間にコレクタ電極にアノード電極
側を接続したダイオードを介挿し、前記第4抵抗器に並
列にコンデンサを接続してなる請求項1記載の残留電荷
放電回路。2. A diode in which an anode electrode side is connected to a collector electrode is inserted between a collector electrode and a fourth resistor of the PNP transistor, and a capacitor is connected in parallel to the fourth resistor. 1. The residual charge discharging circuit described in 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6001877A JPH07210112A (en) | 1994-01-13 | 1994-01-13 | Residual charge discharging circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6001877A JPH07210112A (en) | 1994-01-13 | 1994-01-13 | Residual charge discharging circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07210112A true JPH07210112A (en) | 1995-08-11 |
Family
ID=11513796
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6001877A Pending JPH07210112A (en) | 1994-01-13 | 1994-01-13 | Residual charge discharging circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07210112A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5909199A (en) * | 1994-09-09 | 1999-06-01 | Sony Corporation | Plasma driving circuit |
JP2002149080A (en) * | 2000-11-08 | 2002-05-22 | Nec Corp | Plasma display module provided with power source |
KR100389019B1 (en) * | 2000-11-22 | 2003-06-25 | 엘지전자 주식회사 | Reset Circuit in Plasma Display Panel |
KR100450218B1 (en) * | 2001-10-16 | 2004-09-24 | 삼성에스디아이 주식회사 | A driving apparatus of plasma display panel and the method thereof |
KR100549084B1 (en) * | 1998-08-17 | 2006-03-28 | 삼성전자주식회사 | Display device with transient elimination circuit |
KR100735478B1 (en) * | 2006-05-02 | 2007-07-03 | 삼성전기주식회사 | Power supply for pdp |
KR100744938B1 (en) * | 2006-06-28 | 2007-08-01 | 삼성전기주식회사 | Power supply for plasma display panel |
-
1994
- 1994-01-13 JP JP6001877A patent/JPH07210112A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5909199A (en) * | 1994-09-09 | 1999-06-01 | Sony Corporation | Plasma driving circuit |
KR100549084B1 (en) * | 1998-08-17 | 2006-03-28 | 삼성전자주식회사 | Display device with transient elimination circuit |
JP2002149080A (en) * | 2000-11-08 | 2002-05-22 | Nec Corp | Plasma display module provided with power source |
KR100389019B1 (en) * | 2000-11-22 | 2003-06-25 | 엘지전자 주식회사 | Reset Circuit in Plasma Display Panel |
KR100450218B1 (en) * | 2001-10-16 | 2004-09-24 | 삼성에스디아이 주식회사 | A driving apparatus of plasma display panel and the method thereof |
KR100735478B1 (en) * | 2006-05-02 | 2007-07-03 | 삼성전기주식회사 | Power supply for pdp |
KR100744938B1 (en) * | 2006-06-28 | 2007-08-01 | 삼성전기주식회사 | Power supply for plasma display panel |
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