KR20040087420A - Method and Apparatus of Energy Recovery - Google Patents

Abstract

PURPOSE: An apparatus and a method for recovering an energy are provided to generate a stable discharge as well as to realize a high speed addressing by rapidly rising the voltage of the panel capacitor to the address voltage. CONSTITUTION: An apparatus(64) for recovering an energy includes a capacitive load, an inductor(L), an energy recovery capacitor(Cs), a first diode(D1), a second diode(D2), a first switch(S3) and a second switch(S2). The capacitive load equivalently forms on the discharge cells. The inductor(L) forms the resonance circuit together with the capacitive load. The energy recovery capacitor(Cs) is charged by recovering the energy of the capacitive load. The first diode(D1) is installed on the discharge path of the energy recovery capacitor(Cs). The second diode(D2) and the first switch(S3) are installed on the charge path of the energy recovery capacitor(Cs). And, the second switch(S2) is installed between the inductor(L) and the capacitive load to discharge the voltage charged on the energy recovery capacitor(Cs) as well as is turned on simultaneously.

Description

Power recovery device and power recovery method {Method and Apparatus of Energy Recovery}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power recovery device and a power recovery method, and more particularly, to a power recovery device and a power recovery method capable of generating a stable discharge and enabling high speed addressing.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when ultraviolet light generated by gas discharge excites the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a discharge cell of a conventional AC surface discharge plasma display panel.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 12Y and a sustain electrode 12Z formed on an upper substrate 10, and an address electrode formed on a lower substrate 18. 20X). The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in a direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Referring to FIG. 2, in the conventional AC surface discharge type driving device, m × n discharge cells 1 have scan electrode lines Y1 to Ym, sustain electrode lines Z1 to Zm, and address electrode lines. PDP 30 arranged in a matrix so as to be connected to the electrodes X1 to Xn, the scan driver 32 for driving the scan electrode lines Y1 to Ym, and the sustain electrode lines Z1 to Zm. A sustain driver 34 for driving the < RTI ID = 0.0 > and < / RTI > odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and even-numbered address electrode lines X2, X4, ... First and second address drivers 36A and 36B for dividing and driving Xn) are provided.

The scan driver 32 sequentially supplies scan pulses and sustain pulses to the scan electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × n discharge cells are provided. (1) Let the discharge in each last. The sustain driver 34 supplies a sustain pulse to all of the sustain electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supply image data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, and the second address driver 36B supplies the even-numbered address electrode lines ( Image data is supplied to X2, X4, ..., Xn-2, Xn).

In the AC surface discharge PDP thus driven, a high voltage of several hundred volts or more is required for the address discharge and the sustain discharge. Accordingly, in order to minimize the driving power required for the address discharge and the sustain discharge, a power recovery device is provided in the scan driver 32, the sustain driver 34, and the address drivers 36A, 36B. The power recovery device recovers the voltage charged in the panel and reapplies it as the driving voltage at the next discharge.

3 is a view showing a conventional power recovery device installed in front of the address driver.

Referring to FIG. 3, a conventional power recovery device 40 includes an inductor L connected between a first address driver 36A and an energy recovery capacitor Cs, an energy recovery capacitor Cs, and an inductor ( First and third switches S1 and S3 connected in parallel between L) and second and fourth switches S2 and S4 connected in parallel between the inductor L and the first address driver 36A. It is provided. The panel capacitor Cp equivalently represents the capacitance of the PDP discharge cell.

The second switch S2 is connected to the voltage source Vd, and the fourth switch S4 is connected to the ground voltage source GND. The energy recovery capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during address discharge, and supplies the charged voltage to the panel capacitor Cp again. The energy recovery capacitor Cs charges a voltage of Vd / 2 corresponding to half of the address voltage Vd. The inductor L forms a resonance circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 are turned on and turned off to charge a voltage to the energy recovery capacitor Cs or to supply the charged voltage to the panel capacitor Cp.

The first address driver 36A includes a plurality of fifth and sixth switches S5 and S6. The fifth switch S5 is connected to the power recovery device 40, and the sixth switch S6 is connected to the ground voltage source GND. The fifth switch S5 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied. On the other hand, the power recovery device formed at the front end of the second address driver 36B is formed symmetrically with the first address driver 36A and the power recovery device 40 around the panel capacitor Cp.

4 is a timing diagram illustrating on / off timings of the switches illustrated in FIG. 3 and voltage values supplied to a panel capacitor.

The operation of the power recovery device 40 will be described in detail with reference to FIGS. 3 and 4.

First, it is assumed that the voltage charged to the panel capacitor Cp before the T1 period is 0 volts. It is also assumed that the energy recovery capacitor Cs is charged with a voltage of Vd / 2. In the T1 period, the first and fifth switches S1 and S5 are turned on. At this time, if the discharge cell is not selected, that is, no data pulse is supplied to the address electrode line X, the fifth switch S5 maintains the turn-off state. When the first and fifth switches S1 and S5 are turned on, the first and fifth switches S1 and S5 are turned on from the energy recovery capacitor Cs to the first switch S1, the inductor L, the fifth switch S5, and the panel capacitor Cp. A current pass is formed. Therefore, the voltage charged in the energy recovery capacitor Cs is supplied to the panel capacitor Cp. At this time, since the inductor L and the panel capacitor Cp form a series resonant circuit, the panel capacitor Cp is supplied with a voltage of Vd.

In the T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, the voltage of the address voltage source Vd is supplied to the panel capacitor Cp. The address voltage Vd supplied in the T2 period prevents the voltage of the panel capacitor Cp from falling below the address voltage Vd, and thus stable address discharge can occur. On the other hand, since the voltage of the panel capacitor Cp rises to the address voltage Vd during the T1 period, the driving power supplied from the outside to cause the address discharge is minimized.

In the T3 period, the first switch S1 is turned off and the second switch S2 is turned on. Therefore, the panel capacitor Cp maintains the address voltage Vd for the period T3.

In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the energy recovery capacitor Cs through the fifth switch S5, the inductor L, and the third switch S3. Thus, the voltage charged in the panel capacitor Cp is recovered to the energy recovery capacitor Cs.

In the T5 period, the third and fifth switches S3 and S5 are turned off, and the fourth and sixth switches S4 and S6 are turned on. When the fourth and sixth switches S4 and S6 are turned on, a current path is formed between the base voltage source GND and the panel capacitor Cp to lower the voltage of the panel capacitor Cp to 0 volts. In fact, the conventional power recovery device supplies the data pulse to the panel capacitor Cp while repeating the operation process of T1 to T5.

However, since the data pulse supplied from the conventional power recovery device has a wide pulse width, high speed addressing is impossible. This will be described in detail with reference to FIG. 5. First, a data pulse supplied from a conventional power recovery device includes a period T1 during which a voltage is charged in the panel capacitor Cp, a period T2 during which an address voltage is supplied to the panel capacitor Cp, and a panel It is divided into a period T3 for recovering the voltage charged in the capacitor Cp and charging it in the energy recovery capacitor Cs, and a period T4 for lowering the voltage of the panel capacitor Cp to 0 volts.

Here, the period required for the actual address discharge is the T2 period, and the T1, T3, and T4 periods are preliminary sections for charging the capacitors Cs and Cp. In other words, conventionally, high speed addressing is not possible by the preliminary sections T1, T3, and T4 except for the T2 period required for the actual address discharge.

In order to solve this problem, the applicant has proposed a power recovery device 50 as shown in FIG.

Referring to FIG. 6, the power recovery device 50 includes an inductor L connected between the first address driver 36A and an energy recovery capacitor Cs, an energy recovery capacitor Cs, and an inductor L. FIG. 1st switch S1 connected between them, and 2nd and 3rd switches S2 and S3 connected in parallel between the inductor L and the 1st address drive part 36A.

The second switch S2 is connected to the address voltage source Vd, and the third switch S3 is connected to the base voltage source GND. The energy recovery capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp, and supplies the charged voltage to the panel capacitor Cp again. The inductor L forms a resonance circuit together with the panel capacitor Cp. The first to third switches S1 to S3 are turned on and turned off to charge a voltage to the energy recovery capacitor Cs or to supply the charged voltage to the panel capacitor Cp.

The first address driver 36A includes a plurality of fourth and fifth switches S4 and S5. The fourth switch S4 is connected to the power recovery device 50, and the fifth switch S5 is connected to the ground voltage source GND. The fourth switch S4 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied. On the other hand, the power recovery device formed at the front end of the second address driver 36B is formed symmetrically with the first address driver 36A and the power recovery device 40 around the panel capacitor Cp.

An operation process of the power recovery device shown in FIG. 6 will be described in detail with reference to FIG. 7.

First, it is assumed that the voltage charged to the panel capacitor Cp before the T1 period is 0 volts and the voltage Vd / 2 is charged to the energy recovery capacitor Cs.

In the T1 period, the first and fourth switches S1 and S4 are turned on. At this time, if the discharge cell is not selected, that is, if no data pulse is supplied to the panel capacitor Cp, the fourth switch S4 maintains the turn-off state. When the first and fourth switches S1 and S4 are turned on, the first and fourth switches S1 and S4 are turned on from the energy recovery capacitor Cs to the first switch S1, the inductor L, the fourth switch S4, and the panel capacitor Cp. A current pass is formed. At this time, since the inductor L and the panel capacitor Cp form a series resonant circuit, an address voltage Vd is supplied to the panel capacitor Cp.

In the T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, the address voltage Vd is supplied to the panel capacitor Cp. The address voltage Vd supplied to the panel capacitor Cp prevents the voltage of the panel capacitor Cp from falling below the address voltage Vd so that address discharge occurs normally. At this time, since the voltage of the panel capacitor Cp rises up to the address voltage Vd in the T1 period, the driving power supplied from the outside to generate the address discharge is minimized.

In the T3 period, the first switch S1 is turned off and the address voltage Vd supplied to the panel capacitor Cp is maintained.

In the T4 period, the second switch S2 is turned off and the first switch S1 is turned on. When the first switch S1 is turned on, a current path is formed from the panel capacitor Cp to the fourth switch S4, the inductor L, the first switch S1, and the energy recovery capacitor Cs. The voltage charged in the panel capacitor Cp is recovered to the energy recovery capacitor Cs. That is, during the period T4, the panel capacitor Cp is discharged while the voltage of the panel capacitor Cp is lowered, and at the same time, the voltage Cd is charged to the energy recovery capacitor Cs.

On the other hand, the first switch S1 maintains the turn-on state even after the voltage Vd / 2 is charged in the energy recovery capacitor Cs. Therefore, the voltage charged in the energy recovery capacitor Cs is supplied to the panel capacitor Cp for the period T5. That is, in the power recovery device 50 shown in FIG. 6, as shown in FIG. 8, the period for maintaining the voltage of the energy recovery capacitor Cs at Vd / 2 is eliminated, thereby enabling high speed addressing.

Meanwhile, in FIG. 8, the periods T10 and T12 are preliminary sections for charging / discharging voltages, and T11 is a period for actual discharge. In order to cause stable discharge in the PDP, the T11 period should be set to be longer than a predetermined period. However, if the T11 period is set wide, fast addressing is impossible. In particular, as the PDP becomes larger and larger, this problem becomes more severe.

Accordingly, it is an object of the present invention to provide a power recovery device and a power recovery method that allow stable discharge and high speed addressing.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view showing driving units for driving a conventional plasma display panel.

3 is a view showing a power recovery device of a conventional plasma display panel.

4 is a waveform diagram showing an operation process of the power recovery device shown in FIG.

FIG. 5 is a diagram illustrating a driving voltage generated by the power recovery device shown in FIG. 3.

6 is a view showing a power recovery device of a plasma display panel according to another conventional embodiment.

7 is a waveform diagram showing an operation process of the power recovery device shown in FIG.

FIG. 8 is a diagram illustrating a driving voltage generated by the power recovery device shown in FIG. 6.

9 is a circuit diagram showing a power recovery device according to a first embodiment of the present invention.

10 is a waveform diagram showing an operation process of the power recovery device shown in FIG.

FIG. 11 is a view showing a driving voltage generated by the power recovery device shown in FIG. 9; FIG.

12 is a circuit diagram showing a power recovery device according to a second embodiment of the present invention.

Fig. 13 is a circuit diagram showing a power recovery device according to a third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12Y: sustain electrode 12Z: common electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X: address electrode

24: partition 26: phosphor layer

30 plasma display panel 32 scanning driver

34: sustain driver 36A, 36B, 62, 66: address driver

40,50,60,64: Power recovery device

In order to achieve the above object, the power recovery device of the present invention is charged by recovering the capacitive load equivalently formed in the discharge cell, the inductor for forming a resonance circuit together with the capacitive load, and the energy of the capacitive load. Between the energy recovery capacitor, the first diode provided on the discharge path of the energy recovery capacitor, the second diode and the first switching device provided on the charge path of the energy recovery capacitor, between the inductor and the capacitive load. And a second switching element installed to be connected to the address voltage source and turned on at the same time as the voltage charged in the energy recovery capacitor is discharged.

The first diode is installed so that energy supplied from the energy recovery capacitor can be supplied as a capacitive load.

The second diode is installed so that energy supplied from the capacitive load can be supplied to the energy recovery capacitor.

The first switching element is turned on when the energy recovery capacitor is charged.

The second switching element is turned on for the remaining period except for the period during which the energy recovery capacitor is charged.

Further provided between the first diode and the energy recovery capacitor is provided with a third switching element that always maintains the turn-on state.

A fourth switching device is provided between the inductor and the ground voltage source and is always kept in a turn-off state.

The capacitive load rapidly rises to the voltage of the address voltage source by the voltage supplied from the energy recovery capacitor and the address voltage source at the time of charging, and slowly drops so that the energy recovery capacitor can be charged at the time of discharge.

The power recovery device of the present invention comprises an address voltage source, a supply voltage source having a lower voltage value than the address voltage source, a capacitive load formed equivalently in the discharge cell, an inductor for forming a resonance circuit together with the capacitive load, A first diode and a second diode installed in parallel between the inductor and the supply voltage source, a first switching element provided between the second diode and the supply voltage source, and an inductor and a capacitive load to be connected to an address voltage source And a second switching element that is turned on when the voltage is charged at the load.

The voltage value of the supply voltage source is set to half of the address voltage source.

The first switching element is turned on when the voltage charged with the energy recovery capacitor is supplied to the supply voltage source.

The second switching element is turned on for the remaining time except for the time when the first switching element is turned on.

In the power recovery method of the present invention, the voltage is supplied to the capacitive load equivalently formed in the discharge cell through the charging path, and the voltage of the address voltage source is capacitive while the voltage is supplied to the capacitive load through the charging path. And supplying a load, and recovering the voltage supplied to the capacitive load to the energy recovery capacitor through the discharge path.

When the voltage of the address voltage source is supplied to the capacitive load, the capacitive load rapidly rises to the voltage of the address voltage source.

When the voltage supplied to the capacitive load is recovered by the energy recovery capacitor, the voltage of the capacitive load is slowly lowered.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 9 to 13.

9 is a view showing a power recovery device according to an embodiment of the present invention.

Referring to FIG. 9, the power recovery device 60 according to an embodiment of the present invention includes an inductor L connected between an address driver 62 and an energy recovery capacitor Cs, and an energy recovery capacitor Cs. First and third switches S1 and S3 connected in parallel between the inductor and the inductor L, a first diode D1 connected between the first switch S1 and the inductor L, and a third switch. A second diode D2 connected between S3 and the inductor L, and second and fourth switches S2 and S4 connected in parallel between the inductor L and the address driver 62; . The panel capacitor Cp equivalently represents the capacitance of the PDP discharge cell.

The second switch S2 is connected to the address voltage source Vd, and the fourth switch S4 is connected to the base voltage source GND. Here, the fourth switch S4 always maintains the turn-off state in the normal operation of the power recovery device 60. The third switch S3 is turned on when the voltage charged in the panel capacitor Cp is recovered to the energy recovery capacitor Cs. The first switch S1 always maintains a turn-on state in the normal operation of the power recovery device 60. The first and second diodes D1 and D2 prevent the flow of reverse current.

The energy recovery capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during address discharge, and supplies the charged voltage to the panel capacitor Cp again. The energy recovery capacitor Cs charges a voltage of Vd / 2 corresponding to half of the address voltage Vd. The inductor L forms a resonance circuit together with the panel capacitor Cp.

The address driver 62 includes a plurality of fifth and sixth switches S5 and S6. The fifth switch S5 is connected to the power recovery device 60, and the sixth switch S6 is connected to the ground voltage source GND. The fifth switch S5 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied.

FIG. 10 is a timing diagram illustrating on / off timing of the switches illustrated in FIG. 9 and voltage values supplied to a panel capacitor.

9 and 10 will be described in detail the operation of the power recovery device 60.

First, it is assumed that the voltage charged to the panel capacitor Cp before the T1 period is 0 volts. It is also assumed that the energy recovery capacitor Cs is charged with a voltage of Vd / 2. Here, in the normal operation of the power recovery device 60, the first switch S1 maintains the turn-on state, and the fourth switch S4 maintains the turn-off state.

In the T1 period, the second and fifth switches S2 and S5 are turned on. In this case, if the discharge cell is not selected, that is, if no data pulse is supplied to the panel capacitor Cp, the fifth switch S5 maintains the turn-off state. First, since the first switch S1 is always turned on, the voltage charged in the energy recovery capacitor Cs is supplied to the panel capacitor Cp. Here, since the inductor L and the panel capacitor Cp form a series resonant circuit, the address voltage Vd is supplied to the panel capacitor Cp.

In addition, since the second switch S2 is turned on during the T1 period, the voltage of the address voltage source Vd is supplied to the panel capacitor Cp. That is, the voltage of the energy recovery capacitor Cs and the voltage of the address voltage source Vd are supplied to the panel capacitor Cp during the T1 period. Here, when the voltage of the address voltage source Vd is directly supplied to the panel capacitor Cp, the panel capacitor Cp rises up to the address voltage Vd without a preliminary section that gradually rises. This T1 period lasts until a stable address discharge occurs in the panel capacitor Cp, that is, the discharge cell. Meanwhile, the voltage of the address voltage source Vd is not supplied to the source capacitor Cs by the first diode D1.

In the T2 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, the energy recovery capacitor Cs is applied from the panel capacitor Cp through the fifth switch S5, the inductor L, the second diode D2, and the third switch S3. A current path leading to C1 is formed so that the voltage charged in the panel capacitor Cp is recovered to the energy recovery capacitor Cs.

On the other hand, since the first switch S1 is always turned on, the voltage charged in the energy recovery capacitor Cs is supplied to the panel capacitor Cp again (T1 period). When the voltage charged in Cs is supplied to the panel capacitor Cp, the second switch S2 is also turned on. In fact, in the present invention, the voltage is supplied to the panel capacitor Cp by repeating the periods T1 and T2.

That is, in the power recovery device 60 according to the embodiment of the present invention, since the voltage of the panel capacitor Cp rises rapidly to Vd without a gently rising period as shown in FIG. This becomes possible. Further, since the T1 period used for the actual discharge is set wide, stable address discharge can be caused in the discharge cell.

12 is a view showing a power recovery device according to another embodiment of the present invention.

Referring to FIG. 12, the power recovery device 64 according to another embodiment of the present invention includes an inductor L connected between an address driver 66 and an energy recovery capacitor Cs, and an energy recovery capacitor Cs. ) And a third switch S3 connected between the first diode D1 and the second diode D2 connected in parallel between the inductor L and the second diode D2 and the energy recovery capacitor Cs. ) And a second switch S2 connected between the inductor L and the address driver 66. The panel capacitor Cp equivalently represents the capacitance of the PDP discharge cell.

The second switch S20 is connected to the address voltage source Vd. The first diode D1 passes the current supplied from the energy recovery capacitor Cs and blocks the current supplied from the inductor L. The second diode D2 passes the current supplied from the inductor L and blocks the current supplied from the energy recovery capacitor Cs. The third switch S3 is turned on when the voltage is recovered to the energy recovery capacitor Cs.

The energy recovery capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during address discharge, and supplies the charged voltage to the panel capacitor Cp again. The energy recovery capacitor Cs charges a voltage of Vd / 2 corresponding to half of the address voltage Vd. The inductor L forms a resonance circuit together with the panel capacitor Cp.

The address driver 62 includes a plurality of fifth and sixth switches S5 and S6. The fifth switch S5 is connected to the power recovery device 60, and the sixth switch S6 is connected to the ground voltage source GND. The fifth switch S5 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied.

When comparing the power recovery device 64 according to another embodiment of the present invention with the power recovery device 60 shown in FIG. 9, the first switch S1 and the power recovery device 60 shown in FIG. It can be seen that the fourth switch S4 has been removed. In other words, in the power recovery device 64 according to another embodiment of the present invention, the manufacturing cost may be reduced by removing the first switch S4 which is always turned on and the fourth switch S4 which is always turned off. Can be. In the present invention, instead of the energy recovery capacitor Cs, as shown in FIG. 13, a voltage source of Vd / 2 having a voltage value of half of the address voltage source Vd may be provided. The voltage source of Vd / 2 supplies the voltage value of Vd / 2 to the panel capacitor Cp instead of the energy recovery capacitor Cs. In fact, the operation process of the power recovery device 64 shown in Figs. 12 and 13 is the same as the embodiment of the present invention shown in Figs. 9 and 10 will not be described in detail the detailed operation process.

As described above, according to the power recovery device and the power recovery method according to the present invention, since the charging voltage of the energy recovery capacitor and the voltage of the address voltage source are supplied to the panel capacitor, the panel capacitor suddenly rises to the address voltage. High speed addressing is possible. In addition, since the voltage of the panel capacitor rapidly rises up to the address voltage, the period used for the actual discharge can be set wide to cause stable address discharge.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

A capacitive load equivalently formed in the discharge cell, An inductor for forming a resonance circuit together with the capacitive load; An energy recovery capacitor which is charged by recovering energy of the capacitive load; A first diode provided on a discharge path of the energy recovery capacitor; A second diode and a first switching element installed on a charging path of the energy recovery capacitor; And a second switching element installed between the inductor and the capacitive load so as to be connected to an address voltage source, the second switching element being turned on at the same time as the voltage charged in the energy recovery capacitor is discharged. The method of claim 1, And the first diode is installed so that energy supplied from the energy recovery capacitor can be supplied to the capacitive load. The method of claim 1, And the second diode is installed such that energy supplied from the capacitive load can be supplied to the energy recovery capacitor. The method of claim 1, And the first switching element is turned on when the energy recovery capacitor is charged. The method of claim 1, And the second switching element maintains a turn-on state for a period other than a period during which the energy recovery capacitor is charged. The method of claim 1, And a third switching element installed between the first diode and the energy recovery capacitor to maintain a turn-on state at all times. The method of claim 1, And a fourth switching element installed between the inductor and the base voltage source to maintain a turn-off state at all times. The method of claim 1, The capacitive load is rapidly increased to the voltage of the address voltage source by the voltage supplied from the energy recovery capacitor and the address voltage source at the time of charging, and gently lowered so that the energy recovery capacitor can be charged at the time of discharge. Power recovery device. An address voltage source, A supply voltage source having a voltage value lower than that of the address voltage source; A capacitive load equivalently formed in the discharge cell, An inductor for forming a resonance circuit together with the capacitive load; A first diode and a second diode installed in parallel between the inductor and the supply voltage source; A first switching element provided between the second diode and the supply voltage source; And a second switching element installed between the inductor and the capacitive load so as to be connected to the address voltage source and turned on when a voltage is charged at the capacitive load. The method of claim 9, And the voltage value of the supply voltage source is set to half of the address voltage source. The method of claim 9, And the first switching device is turned on when the voltage charged by the energy recovery capacitor is supplied to the supply voltage source. The method of claim 11, And the second switching element is turned on for the remaining time except for the time when the first switching element is turned on. Supplying a voltage to a capacitive load equivalently formed in the discharge cell through the charging path; Supplying a voltage of an address voltage source to the capacitive load while supplying a voltage to the capacitive load through the charging path; And recovering the voltage supplied to the capacitive load to an energy recovery capacitor through a discharge path. The method of claim 13, And when the voltage of the address voltage source is supplied to the capacitive load, the capacitive load rapidly rises to the voltage of the address voltage source. The method of claim 13, And when the voltage supplied to the capacitive load is recovered by the energy recovery capacitor, the voltage of the capacitive load is gently lowered.