KR100330032B1 - Energy Recovery Apparatus and Method of Addressing Cells using the same in Plasma Display Panel - Google Patents

Abstract

The present invention relates to a power recovery device of a plasma display panel that can perform high-speed addressing and reduce power consumption.

The power recovery device of the plasma display panel of the present invention is characterized in that the amount of voltage charged in the power recovery device is adjusted according to the amount of change in data.

According to the present invention, since the voltage charged in the energy recovery capacitor is determined according to the address data supplied to the address electrode lines, it is possible to reduce the consumption of power consumed by unnecessary switching operation of the power recovery device and to provide high-speed addressing. It is possible.

Description

Power recovery device of plasma display panel and high speed addressing method using same {Energy Recovery Apparatus and Method of Addressing Cells using the same in Plasma Display Panel}

The present invention relates to a power recovery device of a plasma display panel that can perform high-speed addressing and reduce power consumption. The present invention also relates to a fast addressing method using the power recovery device.

Plasma Display Panel (hereinafter referred to as 'PDP') is a display device using visible light generated from a phosphor when ultraviolet rays generated by gas discharge excite the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a conventional AC surface discharge PDP.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 12Y and the common sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Referring to FIG. 2, a conventional AC surface discharge type PDP driving apparatus includes m / n discharge cells 1 having scan / sustain electrode lines Y1 to Ym, common sustain electrode lines Z1 to Zm, and A PDP 30 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 32 for driving the scan / sustain electrode lines Y1 to Ym, and a common sustain; The common sustain driver 34 for driving the electrode lines Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and the even-numbered address electrode lines X2. First and second address drivers 36A and 36B for dividing and driving .X4, ..., Xn-2, Xn are provided. The scan / sustain driver 32 sequentially supplies scan pulses and sustain pulses to the scan / sustain electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × n The discharge in each of the four discharge cells 1 is continued. The common sustain driver 34 supplies a sustain pulse to all of the common sustain electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supply image data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, and the second address driver 36B supplies the even-numbered address electrode lines ( Image data is supplied to X2, X4, ..., Xn-2, Xn).

In the AC surface discharge PDP thus driven, a high voltage of several hundred volts or more is required for the address discharge and the sustain discharge. Accordingly, in order to minimize the driving power required for the address discharge and the sustain discharge, a power recovery device is added to the scan / sustain driver 32, the common sustain driver 34, and the address drivers 36A and 36B. The power recovery apparatus recovers the voltage charged between the scan / sustain electrode line (Y) and the common sustain electrode line (Z) and the voltage charged between the address electrode lines (X) and reuses it as a driving voltage at the next discharge. .

3 is a diagram illustrating a conventional power recovery device installed at the front end of the scan / sustain driver.

Referring to FIG. 3, the conventional power recovery device 38 includes an inductor L connected between the scan / sustain driver 32 and an energy recovery capacitor Cs, an energy recovery capacitor Cs, and an inductor ( First and third switches S1 and S3 connected in parallel between L) are provided. The scan / sustain driver 32 is composed of second and fourth switches S2 and S4 connected in parallel between the panel capacitor Cp and the inductor L. The panel capacitor Cp equivalently represents the capacitance formed between the scan / sustain electrode line Y and the common sustain electrode line Z. FIG. The second switch S2 is connected to the sustain voltage source Vsus, and the fourth switch S4 is connected to the ground voltage source GND. The energy recovery capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during the sustain discharge, and supplies the charged voltage to the panel capacitor Cp again. The energy recovery capacitor Cs has a very large capacitance value to charge a voltage of Vsus / 2 corresponding to half of the sustain voltage Vsus. The inductor L forms a resonance circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 control the flow of current. The power recovery device 38 formed in the common sustain driver 34 is formed symmetrically with the scan / sustain driver 32 around the panel capacitor Cp.

4 is a timing diagram and waveform diagrams illustrating on / off timings of the switches illustrated in FIG. 3 and output waveforms of panel capacitors.

The operation of the power recovery device 38 will be described with reference to FIGS. 3 and 4. First, it is assumed that the voltage charged between the scan / sustain electrode line Y and the common sustain electrode line Z, that is, the voltage charged to the panel capacitor Cp, before the T1 period is 0 volts. It is also assumed that the energy recovery capacitor Cs is charged with a voltage of Vsus / 2. In the T1 period, the first switch S1 is turned on to form a current path from the energy recovery capacitor Cs to the first switch S1, the inductor L, and the panel capacitor Cp. do. At this time, the inductor L and the panel capacitor Cp form a series resonant circuit. Since the voltage Csus / 2 is charged in the energy recovery capacitor Cs, the current charge / charge of the inductor L is performed in the series resonant circuit. The discharge causes the voltage of the panel capacitor Cp to rise to Vsus which is twice the voltage of the energy recovery capacitor Cs. In the period T2, the second switch S2 is turned on. When the second switch S2 is turned on, the sustain voltage Vsus is supplied to the scan / sustain electrode line Y. The sustain voltage Vsus supplied to the scan / sustain electrode line Y prevents the voltage of the panel capacitor Cp from falling below the sustain voltage Vsus so that the sustain discharge occurs normally. At this time, since the voltage of the panel capacitor Cp rises to Vsus in the T1 period, the driving power supplied from the outside to minimize the sustain discharge is minimized. In the T3 period, the first switch S1 is turned off and maintains the sustain voltage Vsus supplied to the scan / sustain electrode line Y. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the energy recovery capacitor Cs through the inductor L and the third switch S3 to form the panel capacitor Cp. The charged voltage is recovered to the energy recovery capacitor Cs. As the panel capacitor Cp is discharged, the voltage of the panel capacitor Cp is lowered, and at the same time, the voltage Csus is charged to the energy recovery capacitor Cs. After the voltage Vsus / 2 is charged in the energy recovery capacitor Cs, the third switch S3 is turned off and the fourth switch S4 is turned on. In the period T5 when the fourth switch S4 is turned on, a current path is formed from the panel capacitor Cp to the base voltage source GND, so that the voltage of the panel capacitor Cp drops to zero volts. In the T6 period, the state of the T5 period is maintained for a predetermined time. The AC drive pulses supplied to the actual scan / sustain electrode line Y and the common sustain electrode line Z are obtained by periodically repeating the operation process for the periods T1 to T6.

5 is a view showing a conventional power recovery device installed in front of the address driver.

Referring to FIG. 5, the conventional power recovery device 40 includes an inductor L connected between the first address driver 36A and an energy recovery capacitor Cs, an energy recovery capacitor Cs, and an inductor ( First and third switches S1 and S3 connected in parallel between L) and second and fourth switches S2 and S4 connected in parallel between the inductor L and the first address driver 36A. It is provided. The first address driver 36A includes fifth and sixth switches S5 and S6 connected between the power recovery device 40 and the panel capacitor Cp. The panel capacitor Cp equivalently represents the capacitance formed between the address electrode lines X1 to X2. The second switch S2 is connected to the voltage source Vd, and the fourth and sixth switches S4 and S6 are connected to the ground voltage source GND. The energy recovery capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during address discharge, and supplies the charged voltage to the panel capacitor Cp again. The energy recovery capacitor Cs has a large capacitance so as to charge a voltage of Vd / 2 corresponding to half of the address voltage Vd. The inductor L forms a resonance circuit together with the panel capacitor Cp. The fifth switch S5 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied. The power recovery device formed at the front end of the second address driver 36B is formed symmetrically with the first address driver 36A and the power recovery device 40 around the panel capacitor Cp.

FIG. 6 is a timing diagram and waveform diagrams illustrating on / off timings of the switches illustrated in FIG. 5 and output waveforms of the panel capacitor.

5 and 6 will be described in the operation of the power recovery device 40. First, it is assumed that the voltage charged between the address electrode lines X before the T1 period, that is, the voltage charged in the panel capacitor Cp is 0 volts. It is also assumed that the energy recovery capacitor Cs is charged with a voltage of Vd / 2. In the T1 period, the first and fifth switches S1 and S5 are turned on. At this time, if the discharge cell is not selected, that is, no data pulse is supplied to the address electrode line X, the fifth switch S5 maintains the turn-off state. When the first and fifth switches S1 and S5 are turned on, the first and fifth switches S1 and S5 are turned on from the energy recovery capacitor Cs to the first switch S1, the inductor L, the fifth switch S5, and the panel capacitor Cp. A current pass is formed. At this time, the inductor L and the panel capacitor Cp form a series resonant circuit. Since the energy recovery capacitor Cs is charged with a voltage of Vd / 2, the voltage of the panel capacitor Cp is caused by the current charge / discharge of the inductor L in the series resonant circuit. The address voltage Vd is doubled. In the T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, the address voltage Vd is supplied to the address electrode line X. The address voltage Vd supplied to the address electrode line X prevents the voltage of the panel capacitor Cp from falling below the address voltage Vd so that address discharge occurs normally. At this time, since the voltage of the panel capacitor Cp rises up to the address voltage Vd in the T1 period, the driving power supplied from the outside to generate the address discharge is minimized. In the T3 period, the first switch S1 is turned off and the address voltage Vd supplied to the address electrode line X is maintained. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the energy recovery capacitor Cs through the fifth switch S5, the inductor L, and the third switch S3. Thus, the voltage charged in the panel capacitor Cp is recovered to the energy recovery capacitor Cs. As the panel capacitor Cp is discharged, the voltage of the panel capacitor Cp drops, and at the same time, the voltage Cd is charged in the energy recovery capacitor Cs. In the T5 period, the third and fifth switches S3 and S5 are turned off, and the fourth and sixth switches S4 and S6 are turned on. When the fourth and sixth switches S4 and S6 are turned on, a current path is formed between the base voltage source GND and the panel capacitor Cp to lower the voltage of the panel capacitor Cp to 0 volts. That is, since the fourth switch S4 is turned off and connected to the ground voltage source GND, the energy recovery capacitor Cs is charged with Vd / 2 which is an intermediate value between the address voltage Vd and the ground voltage source GND. . If a data pulse is supplied in the next address period, the operation of T1 to T5 is repeated. The data pulses supplied to the actual address electrode lines X are obtained by periodically repeating the operation process for the periods T1 to T5.

In the conventional AC surface discharge PDP driven as described above, an address section is used at 2.5 ms or more. However, in the case where the pulse width Td of the address discharge pulse is increased to 2.5 ms or more, the ratio of sustain period which determines the brightness of the actual screen in one frame is 30 in the state that the duration of one frame is fixed to 16.67 ms. Falls below% In addition, in the current PDP driving method, the number of subfields per frame is increased from 8 to 10 to 12 in order to reduce contour noise generated in a moving picture. However, when the number of subfields increases during a fixed frame period, the period of each subfield is shortened by that much. Even in this case, the address period is fixed for each subfield for stable discharge, and only the sustain period is shortened. In a high-resolution PDP with an increased number of scan / sustain electrode lines, the sustain period becomes too short and the display itself becomes impossible. In the high resolution PDP, since the number of scan / sustain electrode lines increases, the address period in which the scan / sustain electrode lines are sequentially driven in each subfield becomes longer. Accordingly, the sustain period is inevitably reduced during the fixed one frame period. In order to solve this problem, fast addressing is required.

7 is a waveform diagram showing a conventional data pulse.

Referring to FIG. 7, the conventional data pulse recovers the voltage charged in the panel capacitor Cp, the period T1 during which the voltage is charged to the panel capacitor Cp, the period T2 during which the data pulse is supplied to the address electrode line X, and the like. T3 period for charging the energy recovery capacitor Cs, and T4 period for decreasing the voltage of the panel capacitor Cp to 0 volts. At this time, the period required for the actual address discharge is the T2 period, and the T1, T3, and T4 periods are preliminary sections for charging the capacitors Cs and Cp. Such spare sections T1, T3, and T4 occupy a greater proportion as fast addressing. That is, while the period T2, which is a period required for the actual address discharge, is reduced, the preliminary sections T1, T3, and T4 for charging the capacitors Cs and Cp are not reduced. Therefore, high speed addressing for a predetermined time or less is impossible by the preliminary sections T1, T3, and T4 for charging the capacitors Cs and Cp. In addition, the conventional power recovery apparatus 40 may reduce the amount of power consumed when there is a large change in data supplied to the address electrode lines X, but full white and blank data without any change in the data may be used. In the case of (Blank Data), power is wasted due to unnecessary switch operation of the power recovery device. That is, in the case of full white, address data must be supplied to all address electrode lines X. When address data is supplied to all such address electrode lines X, the address driver should always output a data pulse. However, even in such a case, since the power recovery device 40 performs unnecessary switching operations, a lot of power is wasted. Therefore, conventionally, data is checked and the power recovery device 40 is not operated in case of full white and blank data. However, since the power recovery device 40 can be turned on / off only in the case of full white and blank data among various data, unnecessary power is consumed in many parts.

Accordingly, an object of the present invention is to provide a power recovery device of a plasma display panel that can perform high-speed addressing and reduce power consumption.

Another object of the present invention is to provide a fast addressing method using the power recovery device.

1 is a perspective view showing a conventional AC surface discharge PDP.

FIG. 2 is a plan view showing an arrangement of electrode lines and discharge cells of the PDP shown in FIG. 1; FIG.

3 is a view showing a conventional power recovery device installed at the front end of the sustain drive unit.

FIG. 4 is a timing diagram and waveform diagram showing on / off timing of the switches shown in FIG. 3 and an output waveform of the panel capacitor. FIG.

5 is a view showing a conventional power recovery device installed in front of the address driver.

FIG. 6 is a timing diagram and waveform diagram showing on / off timing of the switches shown in FIG. 5 and an output waveform of the panel capacitor. FIG.

7 is a waveform diagram showing a data pulse generated by the power recovery device shown in FIG.

8 and 10 are views showing a power recovery device of the present invention installed in front of the address driver.

9 is a timing diagram and waveform diagrams showing on / off timing of the switches shown in FIG. 8 and output waveforms of the panel capacitor.

11A and 11B show data supplied to an address electrode line.

12A and 12C are diagrams showing voltage and output data charged in the energy recovery capacitor shown in FIG.

FIG. 13 is a waveform diagram showing data pulses generated by the power recovery device shown in FIG. 8; FIG.

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12Y: scan / sustain electrode 12Z: common sustain electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X: address electrode

24: partition 26: phosphor

30: PDP 32: scan / sustain drive unit

34: common sustain driver 36A: first address driver

36B: second address driver 38, 40, 50: power recovery device

52,56,60: output data 54,58,62: charging voltage

In order to achieve the above object, the power recovery device of the plasma display panel of the present invention is characterized in that the amount of voltage charged in the power recovery device is adjusted according to the amount of change in data.

The fast addressing method using the power recovery device of the present invention includes the step of adjusting the amount of the voltage charged in the power recovery device according to the amount of change in the data.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 13.

8 is a diagram showing a power recovery device of the present invention installed in front of an address driver.

Referring to FIG. 8, the power recovery device 50 of the present invention includes an inductor L connected between the first address driver 36A and an energy recovery capacitor Cs, an energy recovery capacitor Cs, and an inductor. First and third switches S1 and S3 connected in parallel between (L) and a second switch S2 connected between the inductor L and the first address driver 36A. Compared to the conventional power recovery device, it can be seen that in the present invention, only one switch is installed between the inductor L and the first address driver 36A. The first address driver 36A includes fourth and fifth switches S4 and S5 connected between the power recovery device 50 and the panel capacitor Cp. The panel capacitor Cp equivalently represents the capacitance formed between the address electrode lines X. FIG. The second switch S2 is connected to the voltage source Vd, and the fifth switch S5 is connected to the ground voltage source GND. The energy recovery capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during address discharge, and supplies the charged voltage to the panel capacitor Cp again. At this time, the voltage charged in the energy recovery capacitor Cs is changed according to the data supplied. The inductor L forms a resonance circuit together with the panel capacitor Cp. The fourth switch S4 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied. The power recovery device formed at the front end of the second address driver 36B is formed symmetrically with the first address driver 36A and the power recovery device 50 with respect to the panel capacitor Cp.

FIG. 9 is a timing diagram and waveform diagrams illustrating on / off timings of the switches illustrated in FIG. 8 and output waveforms of the panel capacitor.

8 and 9 will be described the operation of the power recovery device 50 according to the present invention. First, it is assumed that the voltage charged between the address electrode lines X before the T1 period, that is, the voltage charged in the panel capacitor Cp is 0 volts. In addition, it is assumed that a predetermined voltage is charged in the energy recovery capacitor Cs. In the T1 period, the first and fourth switches S1 and S4 are turned on. At this time, if the discharge cell is not selected, that is, if no data pulse is supplied to the address electrode line X, the fourth switch S4 maintains the turn-off state. When the first and fourth switches S1 and S4 are turned on, the first and fourth switches S1 and S4 are turned on from the energy recovery capacitor Cs to the first switch S1, the inductor L, the fourth switch S4, and the panel capacitor Cp. A current pass is formed. At this time, the inductor L and the panel capacitor Cp form a series resonant circuit, and the address voltage Vd is supplied to the panel capacitor Cp. In the T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, the address voltage Vd is supplied to the address electrode line X. The address voltage Vd supplied to the address electrode line X prevents the voltage of the panel capacitor Cp from falling below the address voltage Vd so that address discharge occurs normally. In the T3 period, the first switch S1 is turned off and the address voltage Vd supplied to the address electrode line X is maintained. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the energy recovery capacitor Cs through the fourth switch S4, the inductor L, and the third switch S3. The voltage charged in the panel capacitor Cp is recovered to the energy recovery capacitor Cs. As the panel capacitor Cp is discharged, the voltage of the panel capacitor Cp drops, and at the same time, a predetermined voltage is charged in the energy recovery capacitor Cs. In the T5 period, the operation of the T1 period is repeated and the address pulse is supplied to the address electrode line X. The data pulses supplied to the actual address electrode lines X are obtained by periodically repeating the operation process for the periods T1 to T4.

A predetermined number of address electrode lines X are connected to the actual address driver 36A as shown in FIG. 10 to 11b will be described in detail the operation of the power recovery device 50 of the present invention according to the data change.

11A and 11B show address data supplied to the n-th and n-th scan / sustain electrode lines Yn-1, Yn. First, address data is supplied to all the discharge cells of the n-th scan / sustain electrode line Yn-1 in FIGS. 11A and 11B. Thereafter, address data is supplied to some of the discharge cells in the nth scan / sustain electrode line Yn in FIG. 11A. That is, address data is not supplied to the third and n-1th address electrode lines X3 and Xn-1. At this time, the voltage charged in the third and n-1th address electrode lines X3 and Xn-1 to which the address data is not supplied is recovered by the energy recovery capacitor Cs. At this time, the voltage recovered by the energy recovery capacitor Cs is recovered to the energy recovery capacitor Cs via an internal diode (not shown) of the fourth switch S4 formed in the first address driver 36A. In FIG. 11B, address data is not supplied to all the discharge cells of the nth scan / sustain electrode line Yn. When the address data is not supplied in this manner, the voltage charged in the first to nth address electrode lines X1 to Xn is recovered by the energy recovery capacitor Cs. That is, a difference in voltage recovered to the energy recovery capacitor Cs occurs according to the address data supplied to the address electrode lines X. In the conventional power recovery device 40, after the voltage is recovered, the fourth switch S4 shown in FIG. 5 is connected to the ground voltage source GND to maintain the voltage of the energy recovery capacitor Cs at Vd / 2 at all times. . However, in the present invention, since the process of connecting to the electromotive voltage source GND after the voltage is recovered is omitted, a difference in the voltage recovered according to the address data supplied to the address electrode lines X is generated. That is, as shown in FIGS. 11A and 11B, the voltage value charged in the energy recovery capacitor Cs varies according to the change amount of the address data.

12A and 12C are graphs showing voltages charged in an energy recovery capacitor according to a change in address data when the address voltage is assumed to be 60V.

FIG. 12A shows the output data 52 when the address data is supplied to the address electrode line X and the voltage 54 charged in the energy recovery capacitor Cs. When address data is supplied to the address electrode line X in a perverse manner, that is, when the address data is 100% converted, the energy recovery capacitor Cs is charged with 30 V, which is ½ of the address voltage Vd. When the address data is converted into a permutation, the voltage charged in the power recovery device 50 is balanced with the discharged voltage. Thus, the energy recovery capacitor Cs is charged with 30 V, which is ½ of the address voltage Vd.

FIG. 12B shows the voltage 52 charged in the output data 56 and the energy recovery capacitor Cs when the address data supplied to the address electrode line X is 50% converted. When the address data supplied to the address electrode line X is 50% converted, a voltage of about 40V is charged to the energy recovery capacitor Cs. That is, since the change in the address data is smaller than that in FIG. 12A, the voltage 58 charged in the energy recovery capacitor Cs is increased by about 10 V from the charging voltage 54 of FIG. 12A.

FIG. 12B shows the output data 60 when the full white data is supplied to the address electrode line X and the voltage 62 charged in the energy recovery capacitor Cs. When full white data is supplied to the address electrode line X, that is, when there is no change in the address data, the energy recovery capacitor Cs is charged with 60 V, which is the address voltage Vd. When there is no change in data supplied to the address electrode line X, the voltage charged in the panel capacitor Cp is recovered by the energy recovery capacitor Cs, but the voltage charged in the panel capacitor Cp is stored in the energy recovery capacitor ( It is not discharged to Cs). Therefore, since the actual operation of the power recovery device 50 is not performed, the voltage of the energy recovery capacitor Cs increases to the address voltage Vd. That is, the power recovery device 50 of the present invention does not unnecessarily consume power because the operation of the power recovery device 50 is determined according to the address data supplied.

Fig. 13 is a waveform diagram showing a data pulse of the present invention.

Referring to FIG. 13, the data pulse of the present invention is a T1 period in which a voltage is charged in the panel capacitor Cp, a T2 period in which a data pulse is supplied to the address electrode line X, and a voltage charged in the panel capacitor Cp. It is divided into the period T3 which is collected and charged in the energy recovery capacitor Cs. In contrast with the conventional data pulse shown in FIG. 7, it can be seen that in the present invention, the T4 period for maintaining the voltage of the energy recovery capacitor Cs at Vd / 2 is removed. Meanwhile, the fourth switch S4 may be added to the power recovery device 50 of the present invention between the inductor L and the first address driver 36A as shown in FIG. 5. The fourth switch S4 is turned on after one frame to stabilize the operation of the power recovery device.

As described above, according to the power recovery apparatus of the plasma display panel and the high speed addressing method using the same, the voltage charged in the energy recovery capacitor is determined according to the address data supplied to the address electrode lines. Accordingly, by reducing the sustain-down switching operation, which is one step of the driving waveform for energy recovery, the addressing time can be reduced by the time allotted to the sustain down along with component reduction, thereby enabling high-speed driving. Furthermore, since the charge amount of the energy recovery capacitor is automatically adjusted by the data change, power consumption due to unnecessary switching operation can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

An address driver for supplying data to an address electrode line and a power recovery device for recovering a voltage charged in a capacitive load formed between the address electrode lines and charging an external capacitor, The amount of voltage charged in the power recovery device is adjusted according to the amount of change of the data, the power recovery device of the plasma display panel. The method of claim 1, An inductor constituting a resonant circuit together with the capacitive load; And a switching element for supplying the data to the address electrode line by using the resonant circuit so as to omit a reset section for discharging the address electrode line to a ground voltage. . The method of claim 2, The switching device, First and second switching elements connected in parallel between the inductor and the external capacitor; And a third switching element connected between the inductor and the address driver. The method of claim 3, wherein And a fourth switching element connected between the inductor and the address driver and short-circuited between the frame to stabilize the operation of the power recovery device. A high speed addressing method using an address driver for supplying data to an address electrode line, and a power recovery device for recovering a voltage charged in a capacitive load formed between the address electrode lines and charging an external capacitor. And adjusting the amount of the voltage charged in the power recovery device according to the amount of change of the data. The method of claim 5, And a reset section for discharging the address electrode line to a ground voltage is omitted. The method of claim 6, The data is, Charging the capacitive load with voltage; Supplying a predetermined voltage to the address electrode line; And recovering the voltage charged in the capacitive load to charge the external capacitor.