KR100363675B1 - Energy Recovery Apparatus and Method in Plasma Display Panel - Google Patents

Abstract

The present invention relates to a power recovery device of a plasma display panel that can maintain a constant voltage of an external capacitor formed in the power recovery device at all times.

The power recovery device of the plasma display panel according to the present invention maintains a constant voltage level of the external capacitor by supplying an external capacitor for supplying a voltage to the capacitive load equivalently formed between the discharge sustaining electrode lines and the external capacitor. A power supply stabilizer is provided, and the power supply stabilizer is provided with voltage divider resistors for maintaining a constant voltage of the external capacitor by being connected to the external capacitor and dividing the discharge holding voltage to supply the external capacitor.

According to the present invention, it is possible to stably maintain the voltage applied to the external capacitor at a specific voltage level regardless of the change or the external factor of the current supply amount due to the variation in the number of discharges.

Description

Power recovery device and method of plasma display panel {Energy Recovery Apparatus and Method in Plasma Display Panel}

The present invention relates to an apparatus and method for recovering power of a plasma display panel, and more particularly, to an apparatus and method for recovering power of a plasma display panel to maintain a constant voltage of an external capacitor formed in the apparatus.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when ultraviolet light generated by gas discharge excites the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a conventional AC surface discharge PDP.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 12Y and the common sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

2 is a view showing a driving apparatus of a conventional AC surface discharge type PDP.

Referring to FIG. 2, a conventional AC surface discharge type PDP driving apparatus includes m / n discharge cells 1 having scan / sustain electrode lines Y1 to Ym, common sustain electrode lines Z1 to Zm, and A PDP 30 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 32 for driving the scan / sustain electrode lines Y1 to Ym, and a common sustain; The common sustain driver 34 for driving the electrode lines Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and the even-numbered address electrode lines X2. First and second address drivers 36A and 36B for dividing and driving .X4, ..., Xn-2, Xn are provided. The scan / sustain driver 32 sequentially supplies scan pulses and sustain pulses to the scan / sustain electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × n The discharge in each of the four discharge cells 1 is continued. The common sustain driver 34 supplies a sustain pulse to all of the common sustain electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supply image data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, and the second address driver 36B supplies the even-numbered address electrode lines ( Image data is supplied to X2, X4, ..., Xn-2, Xn).

In the AC surface discharge PDP driven as described above, a high voltage of several hundred volts or more is required for sustain discharge. Accordingly, in order to minimize the driving power required for the sustain discharge, a power recovery device is added to the scan / sustain driver 32 and the common sustain driver 34. The power recovery apparatus recovers the voltage charged in the scan / sustain electrode line (Y) and the common sustain electrode line (Z), and reuses it as a driving voltage at the next discharge.

3 is a view showing a conventional power recovery device.

Referring to FIG. 3, the power recovery device 38 installed at the front end of the scan / sustain driver 32 includes an inductor L connected between the panel capacitor Cp and the source capacitor Cs, and a source capacitor Cs. And first and third switches S1 and S3 connected in parallel between and inductor L. The scan / sustain driver 32 has second and fourth switches S2 and S4 connected in parallel between the panel capacitor Cp and the inductor L. The panel capacitor Cp equivalently represents the capacitance formed between the scan / sustain electrode line Y and the common sustain electrode line Z. FIG. The second switch S2 is connected to the sustain voltage source Vsus, and the fourth switch S4 is connected to the ground voltage source GND. The source capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during the sustain discharge, and supplies the charged voltage to the panel capacitor Cp again. The source capacitor Cs has a large capacitance so as to charge a voltage of Vsus / 2 corresponding to half of the sustain voltage Vsus. The inductor L forms a resonance circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 control the flow of current. The power recovery device 38 formed in the common sustain driver 34 is symmetrically formed with respect to the panel capacitor Cp.

4 is a timing diagram and waveform diagrams illustrating on / off timing of the switches illustrated in FIG. 3 and output waveforms of the panel capacitor.

The operation of the power recovery device 38 will be described with reference to FIGS. 3 and 4. First, it is assumed that the voltage charged between the scan / sustain electrode line Y and the common sustain electrode line Z, that is, the voltage charged in the panel capacitor Cp, before the T1 period is 0 volts. In addition, it is assumed that the source capacitor Cs is charged with a voltage of Vsus / 2. In the T1 period, the first switch S1 is turned on to form a current path from the source capacitor Cs to the first switch S1, the inductor L, and the panel capacitor Cp. At this time, the inductor L and the panel capacitor Cp form a series resonant circuit. Since the voltage of Vsus / 2 is charged to the source capacitor Cs, the voltage of the panel capacitor Cp is twice the voltage of the source capacitor Cs by the current charge / discharge of the inductor L in the series resonant circuit. Will rise to (Vsus). In the T2 period, the second switch S2 is turned on to supply the sustain voltage Vsus to the scan / sustain electrode line Y. The sustain voltage Vsus supplied to the scan / sustain electrode line Y prevents the voltage of the panel capacitor Cp from falling below the sustain voltage Vsus so that the sustain discharge occurs normally. At this time, since the voltage of the panel capacitor Cp rises to the sustain voltage Vsus in the T1 period, the driving voltage supplied from the outside to cause the sustain discharge is minimized. In the T3 period, the first switch S1 is turned off and the panel capacitor Cp maintains the sustain voltage Vsus. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the source capacitor Cs through the inductor L and the third switch S3 to charge the panel capacitor Cp. The voltage is recovered to the source capacitor Cs. As the panel capacitor Cp is discharged, the voltage of the panel capacitor Cp drops, and at the same time, the voltage of Vsus / 2 is charged to the source capacitor Cs. After the voltage of Vsus / 2 is charged to the source capacitor Cs, the third switch S3 is turned off and the fourth switch S4 is turned on. In the period T5 when the fourth switch S4 is turned on, a current path is formed from the panel capacitor Cp to the base voltage source GND, so that the voltage of the panel capacitor Cp drops to zero volts. In the T6 period, the state of the T5 period is maintained for a predetermined time. The AC drive pulses supplied to the actual scan / sustain electrode line Y and the common sustain electrode line Z are obtained by periodically repeating the operation process for the periods T1 to T6.

In such a power recovery device, the voltage charged in the source capacitor Cs is at the level of Vsus / 2 such that the peak voltage Vpp of the resonance waveform by the inductor L and the capacitor C is maintained at the sustain voltage Vsus level. Should be kept constant. Only when the voltage level of the source capacitor Vs is maintained at Vsus / 2, the sustain pulse can be stably supplied and the energy recovery efficiency can be maintained at a level satisfactory. However, the charging voltage of the source capacitor Cs may change due to a change in the current supply amount due to a load change of the PDP, for example, a variation in the number of discharges, or an external factor. Particularly, when the voltage of the source capacitor Cs becomes lower than Vsus / 2, the peak value Vpp corresponding to the resonance point of the resonance waveform by the inductor L and the capacitor C decreases, thereby reducing the external sustain voltage. The driving level can be stabilized when the voltage level of (Vsus) is increased. Accordingly, in order to maintain the voltage level of the external sustain voltage Vsus to a minimum and to stabilize the driving of the PDP, a method for maintaining the charging voltage of the source capacitor Cs is required constantly.

Accordingly, an object of the present invention is to provide an apparatus and method for recovering power of a plasma display panel which can maintain a constant voltage of a source capacitor.

1 is a perspective view showing a conventional AC surface discharge PDP.

2 is a view showing a driving apparatus of a conventional AC surface discharge type PDP.

3 is a view showing a conventional power recovery device.

FIG. 4 is a timing diagram and waveform diagram showing on / off timing of the switches shown in FIG. 3 and an output waveform of the panel capacitor. FIG.

5 is a view showing a power recovery device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12Y: scan / sustain electrode 12Z: common sustain electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X: address electrode

24: partition 26: phosphor

30: PDP 32: scan / sustain drive unit

34: common sustain driver 36A: first address driver

36B: second address driver 38, 40: power recovery device

42: power stabilizer

In order to achieve the above object, a power recovery device of a plasma display panel of the present invention includes an external capacitor for supplying a voltage to a capacitive load equivalently formed between discharge sustaining electrode lines, and an external capacitor to supply a voltage to the external capacitor. A power supply stabilizer is provided to maintain a constant voltage level, and the power supply stabilizer is connected to an external capacitor and has voltage divider resistors for maintaining a constant voltage of the external capacitor by dividing a discharge holding voltage to supply the external capacitor. .

In order to achieve the above object, the power recovery method of the plasma display panel of the present invention includes the steps of maintaining the voltage level of the external capacitor at half the discharge sustain voltage during charge and discharge of the external capacitor; And supplying a discharge sustain voltage to the discharge sustain electrode using the voltage of the external capacitor.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIG. 5.

5 is a view showing a power recovery device according to the present invention.

Referring to FIG. 5, the power recovery apparatus 40 according to the present invention includes an inductor L connected between a panel capacitor Cp and a source capacitor Cs, and a source capacitor Cs and an inductor L. First and third switches S1 and S3 connected in parallel and a power supply stabilizer 42 connected to the source capacitor Cs are provided. The power supply stabilizer 42 includes a diode D connected in parallel with the source capacitor Cs, and first and second resistors R1 and R2 connected in parallel with the diode D. FIG. In contrast with the conventional power recovery device 38, it can be seen that the power recovery device 40 of the present invention further includes a power supply stabilizer 42. The scan / sustain driver 32 is composed of second and fourth switches S2 and S4 connected in parallel between the panel capacitor Cp and the inductor L. The panel capacitor Cp equivalently represents the capacitance formed between the scan / sustain electrode line Y and the common sustain electrode line Z. FIG. The second switch S2 and the first resistor R1 are connected to the sustain voltage source Vsus, and the fourth switch S4 and the second resistor R2 are connected to the ground voltage source GND. The first and second resistors R1 and R2 formed in the voltage stabilizer 42 have the same resistance value. Since the first and second resistors R1 and R2 have the same resistance value, a voltage of Vsus / 2 is applied to the node point 44. The voltage of Vsus / 2 applied to the node point 44 is supplied through the diode D to the source capacitor Cs. The source capacitor Cs is charged by the voltage charged to the panel capacitor Cp and the voltage supplied from the power supply stabilizer 42 during the sustain discharge, and supplies the charged voltage to the panel capacitor Cp. The source capacitor Cs has a large capacitance so as to charge a voltage of Vsus / 2 corresponding to half of the sustain voltage Vsus. The inductor L forms a resonance circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 control the flow of current. The power recovery device 40 formed in the common sustain driver 34 is symmetrically formed with the scan / sustain driver 32 around the panel capacitor Cp.

The operation of the power recovery device 40 will be described with reference to FIGS. 4 and 5.

First, it is assumed that the voltage charged between the scan / sustain electrode line Y and the common sustain electrode line Z, that is, the voltage charged to the panel capacitor Cp, before the T1 period is 0 volts. In addition, it is assumed that the source capacitor Cs is charged with a voltage of Vsus / 2. In the T1 period, the first switch S1 is turned on to form a current path from the source capacitor Cs to the first switch S1, the inductor L, and the panel capacitor Cp. At this time, the inductor L and the panel capacitor Cp form a series resonant circuit. Since the voltage of Vsus / 2 is charged to the source capacitor Cs, the voltage of the panel capacitor Cp is twice the voltage of the source capacitor Cs by the current charge / discharge of the inductor L in the series resonant circuit. Will rise to (Vsus). In the T2 period, the second switch S2 is turned on to supply the sustain voltage Vsus to the scan / sustain electrode line Y. The sustain voltage Vsus supplied to the scan / sustain electrode line Y prevents the voltage of the panel capacitor Cp from falling below the sustain voltage Vsus so that the sustain discharge occurs normally. At this time, since the voltage of the panel capacitor Cp increases to the sustain voltage Vsus in the T1 period, the driving power supplied from the outside to minimize the sustain discharge is minimized. In the T3 period, the first switch S1 is turned off and the panel capacitor Cp maintains the sustain voltage Vsus. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the source capacitor Cs through the inductor L and the third switch S3 to charge the panel capacitor Cp. The source capacitor Cs is charged by the voltage of Vsus / 2 supplied from the voltage and power supply stabilizer 42. At this time, when the voltage of Vsus / 2 is charged to the source capacitor Cs, the voltage applied to the node point 44 and the voltage charged to the source capacitor Cs are balanced to turn off the diode D. That is, the source capacitor Cs always maintains a voltage of Vsus / 2. After the voltage of Vsus / 2 is charged to the source capacitor Cs, the third switch S3 is turned off and the fourth switch S4 is turned on. In the period T5 when the fourth switch S4 is turned on, a current path is formed from the panel capacitor Cp to the base voltage source GND, so that the voltage of the panel capacitor Cp drops to zero volts. In the T6 period, the state of the T5 period is maintained for a predetermined time. The AC drive pulses supplied to the actual scan / sustain electrode line Y and the common sustain electrode line Z are obtained by periodically repeating the operation process for the periods T1 to T6.

As described above, according to the power recovery apparatus of the plasma display panel according to the present invention, it is possible to stably maintain the voltage applied to the external capacitor at a specific voltage level regardless of the change or the external factor of the current supply amount due to the variation in the number of discharges. have. Therefore, the voltage level of the external sustain voltage can be kept to a minimum, and the driving of the plasma display panel can be stabilized.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A plasma display panel which supplies a discharge sustain voltage to a discharge sustain electrode line, An external capacitor for supplying a voltage to the capacitive load equivalently formed between the discharge sustaining electrode lines; A power stabilizer for supplying a voltage to the external capacitor to maintain a constant voltage level of the external capacitor, The power stabilizer is connected to the external capacitor and divides the discharge sustain voltage and supplies the external capacitor to the external capacitor to provide voltage divider resistors for maintaining a constant voltage of the external capacitor. Device. The method of claim 1, And the divided resistors supply a voltage corresponding to half of the discharge sustain voltage to the external capacitor. The method of claim 2, And a diode connected between the voltage divider and the external capacitor. A power recovery method for supplying a discharge sustain voltage to the discharge sustain electrode using a plasma display panel including a discharge sustain electrode and a voltage charged in an external capacitor; Maintaining a voltage level of the external capacitor at a specific level when charging and discharging the external capacitor; And supplying a discharge sustaining voltage to the discharge sustaining electrode by using the voltage of the specific level.