KR100371148B1 - Method for manufacturing mos transistor - Google Patents

Method for manufacturing mos transistor Download PDF

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Publication number
KR100371148B1
KR100371148B1 KR1020010035490A KR20010035490A KR100371148B1 KR 100371148 B1 KR100371148 B1 KR 100371148B1 KR 1020010035490 A KR1020010035490 A KR 1020010035490A KR 20010035490 A KR20010035490 A KR 20010035490A KR 100371148 B1 KR100371148 B1 KR 100371148B1
Authority
KR
South Korea
Prior art keywords
gate electrode
silicon layer
drain
upper gate
source
Prior art date
Application number
KR1020010035490A
Other languages
Korean (ko)
Inventor
Seong Do Jeon
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Priority to KR1020010035490A priority Critical patent/KR100371148B1/en
Application granted granted Critical
Publication of KR100371148B1 publication Critical patent/KR100371148B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for manufacturing an MOS transistor is provided to improve current driving capability and punch-through property between source and drain by using a lower and upper gate electrode. CONSTITUTION: A groove is formed by selectively etching an insulating substrate(10). A lower gate electrode(11) is formed in the groove. After forming a lower insulating layer(12) on the lower gate electrode, a silicon layer(13) as a substrate is grown on the lower gate electrode. Ion-implantation processing is performed to control the threshold voltage. After activating ions implanted in the silicon layer(13), an upper gate insulating layer(16) is formed on the silicon layer. After forming a silicon spacer(15) at both sidewalls of the silicon layer(13), an upper gate electrode(17) is formed on the resultant structure. By implanting heavily doped dopants into the silicon layer using the upper gate electrode as a mask, a source/drain(14) is formed in the silicon layer(13). After forming an insulating layer(18) on the resultant structure, contact holes are formed to expose the source/drain. A metal contact(19) is formed in the contact holes. Then, a metal electrode(20) is formed to connect the metal contact(19).
KR1020010035490A 2001-06-21 2001-06-21 Method for manufacturing mos transistor KR100371148B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010035490A KR100371148B1 (en) 2001-06-21 2001-06-21 Method for manufacturing mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010035490A KR100371148B1 (en) 2001-06-21 2001-06-21 Method for manufacturing mos transistor

Publications (1)

Publication Number Publication Date
KR100371148B1 true KR100371148B1 (en) 2003-02-06

Family

ID=37416499

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010035490A KR100371148B1 (en) 2001-06-21 2001-06-21 Method for manufacturing mos transistor

Country Status (1)

Country Link
KR (1) KR100371148B1 (en)

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GRNT Written decision to grant
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