KR100376981B1 - Method for forming transistor in semiconductor device - Google Patents

Method for forming transistor in semiconductor device Download PDF

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Publication number
KR100376981B1
KR100376981B1 KR1020010036604A KR20010036604A KR100376981B1 KR 100376981 B1 KR100376981 B1 KR 100376981B1 KR 1020010036604 A KR1020010036604 A KR 1020010036604A KR 20010036604 A KR20010036604 A KR 20010036604A KR 100376981 B1 KR100376981 B1 KR 100376981B1
Authority
KR
South Korea
Prior art keywords
region
trench
active region
transistor
semiconductor device
Prior art date
Application number
KR1020010036604A
Other languages
Korean (ko)
Inventor
Kil Ho Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Priority to KR1020010036604A priority Critical patent/KR100376981B1/en
Application granted granted Critical
Publication of KR100376981B1 publication Critical patent/KR100376981B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

PURPOSE: A method for forming a transistor in a semiconductor device is provided to improve the operating speed of the transistor by using a gate electrode having narrow channel length. CONSTITUTION: An active region(24) as a source/drain region is formed by implanting heavily doped dopants into the semiconductor substrate(21). A trench is formed by partially etching the active region(24) using a photoresist pattern for defining a gate formation region. An insulating spacer(30) is formed at inner walls of the trench. An inactive region(31) as a channel region is formed by implanting lightly doped dopants into the active region of the lower of the trench. A gate insulating pattern(34) is formed on the trench. After depositing a conductive layer on the gate insulating pattern, a gate electrode(36) having narrow channel length and the same height to the active region(24) is formed by polishing the conductive layer.
KR1020010036604A 2001-06-26 2001-06-26 Method for forming transistor in semiconductor device KR100376981B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010036604A KR100376981B1 (en) 2001-06-26 2001-06-26 Method for forming transistor in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010036604A KR100376981B1 (en) 2001-06-26 2001-06-26 Method for forming transistor in semiconductor device

Publications (1)

Publication Number Publication Date
KR100376981B1 true KR100376981B1 (en) 2003-03-26

Family

ID=37416976

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010036604A KR100376981B1 (en) 2001-06-26 2001-06-26 Method for forming transistor in semiconductor device

Country Status (1)

Country Link
KR (1) KR100376981B1 (en)

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