KR100361534B1 - Method for fabricating transistor - Google Patents

Method for fabricating transistor Download PDF

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Publication number
KR100361534B1
KR100361534B1 KR1020010016310A KR20010016310A KR100361534B1 KR 100361534 B1 KR100361534 B1 KR 100361534B1 KR 1020010016310 A KR1020010016310 A KR 1020010016310A KR 20010016310 A KR20010016310 A KR 20010016310A KR 100361534 B1 KR100361534 B1 KR 100361534B1
Authority
KR
South Korea
Prior art keywords
spacer
layer
insulation layer
gate electrode
region
Prior art date
Application number
KR1020010016310A
Other languages
Korean (ko)
Inventor
Ha Zoong Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Priority to KR1020010016310A priority Critical patent/KR100361534B1/en
Priority to JP2002078145A priority patent/JP2002324811A/en
Priority to US10/103,692 priority patent/US6617229B2/en
Application granted granted Critical
Publication of KR100361534B1 publication Critical patent/KR100361534B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for fabricating a transistor is provided to prevent a short channel effect and improve a current characteristic, by forming a transistor including an oxide layer spacer and a nitride layer spacer that are sequentially formed on a gate electrode, by dry-etching the oxide layer spacer while using the nitride layer spacer as a mask and by implanting ions into a lightly-doped-drain(LDD) region where the oxide layer spacer is etched so that a local LDD region is formed. CONSTITUTION: A gate electrode(15) is formed on a semiconductor substrate(11). A gate protection layer is formed. The LDD region(21) is formed in the surface of the semiconductor substrate at both sides of the gate electrode. A pocket impurity region(23) is formed. The first insulation layer and the second insulation layer are sequentially formed on the gate protection layer such that the first insulation layer has an etch selectivity difference with the gate protection layer and the second insulation layer. The first and second insulation layers are anisotropically etched to form a double spacer composed of the first and second insulation layer spacers. A source/drain region(29) is formed in the surface of the semiconductor substrate at both sides of the gate electrode including the double spacer. The first insulation layer spacer is dry-etched to expose the gate protection layer between the gate electrode and the second insulation layer spacer. The local LDD region(31) is formed in the LDD region.
KR1020010016310A 2001-03-28 2001-03-28 Method for fabricating transistor KR100361534B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020010016310A KR100361534B1 (en) 2001-03-28 2001-03-28 Method for fabricating transistor
JP2002078145A JP2002324811A (en) 2001-03-28 2002-03-20 Transistor having local ldd region and method for manufacturing the same
US10/103,692 US6617229B2 (en) 2001-03-28 2002-03-25 Method for manufacturing transistor of double spacer structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010016310A KR100361534B1 (en) 2001-03-28 2001-03-28 Method for fabricating transistor

Publications (1)

Publication Number Publication Date
KR100361534B1 true KR100361534B1 (en) 2002-11-23

Family

ID=19707541

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010016310A KR100361534B1 (en) 2001-03-28 2001-03-28 Method for fabricating transistor

Country Status (3)

Country Link
US (1) US6617229B2 (en)
JP (1) JP2002324811A (en)
KR (1) KR100361534B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100913323B1 (en) 2002-12-30 2009-08-20 동부일렉트로닉스 주식회사 Method for formung a transistor in a semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275034A1 (en) * 2004-04-08 2005-12-15 International Business Machines Corporation A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance
JP2007165541A (en) * 2005-12-13 2007-06-28 Oki Electric Ind Co Ltd Method for manufacturing semiconductor device
JP4799217B2 (en) * 2006-03-03 2011-10-26 Ｏｋｉセミコンダクタ株式会社 Manufacturing method of semiconductor device
US7855110B2 (en) * 2008-07-08 2010-12-21 International Business Machines Corporation Field effect transistor and method of fabricating same
CN114152857A (en) * 2021-12-07 2022-03-08 华东师范大学 Preparation method of two-dimensional material field effect transistor failure sample

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW301032B (en) * 1996-06-27 1997-03-21 Winbond Electronics Corp Structure of self-aligned salicide device with double sidewall spacers and fabrication method thereof
US6020242A (en) * 1997-09-04 2000-02-01 Lsi Logic Corporation Effective silicide blocking
US5925914A (en) * 1997-10-06 1999-07-20 Advanced Micro Devices Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance
KR100302187B1 (en) * 1997-10-08 2001-11-22 윤종용 Method for fabricating semiconductor device
US6329279B1 (en) * 2000-03-20 2001-12-11 United Microelectronics Corp. Method of fabricating metal interconnect structure having outer air spacer
US6350665B1 (en) * 2000-04-28 2002-02-26 Cypress Semiconductor Corporation Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100913323B1 (en) 2002-12-30 2009-08-20 동부일렉트로닉스 주식회사 Method for formung a transistor in a semiconductor device

Also Published As

Publication number Publication date
JP2002324811A (en) 2002-11-08
US20020142556A1 (en) 2002-10-03
US6617229B2 (en) 2003-09-09

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