KR100350590B1 - 칩 사이즈가 감소된 dram - Google Patents
칩 사이즈가 감소된 dram Download PDFInfo
- Publication number
- KR100350590B1 KR100350590B1 KR1020000066927A KR20000066927A KR100350590B1 KR 100350590 B1 KR100350590 B1 KR 100350590B1 KR 1020000066927 A KR1020000066927 A KR 1020000066927A KR 20000066927 A KR20000066927 A KR 20000066927A KR 100350590 B1 KR100350590 B1 KR 100350590B1
- Authority
- KR
- South Korea
- Prior art keywords
- memory cell
- bank
- cell plates
- pair
- banks
- Prior art date
Links
- 238000000034 method Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000004913 activation Effects 0.000 claims description 2
- 230000009849 deactivation Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 description 4
- 230000001174 ascending effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (6)
- 반도체 메모리 장치에 있어서,각각 다른 하나가 비활성화시에 활성화될 수 있는 한 쌍의 뱅크, 및 다수의 I/O 증폭기(32)를 포함하고 상기 한 쌍의 뱅크에 대해 배치된 I/O 증폭부를 포함하며, 상기 I/O 증폭부는 활성화동안 상기 뱅크 쌍 중 하나의 뱅크에 대한 판독/기입 데이터를 증폭하는 것을 특징으로 하는 반도체 메모리 장치.
- 제1항에 있어서, 상기 뱅크 쌍의 각각의 뱅크는 2개의 메모리 셀 플레이트(11, 12; 13, 14; 15, 16; 17, 18) 또는 그 이상을 포함하고, 상기 뱅크 쌍 중 하나의 뱅크의 상기 메모리 셀 플레이트(11, 12; 13, 14; 15, 16; 17, 18) 각각은 상기 뱅크 쌍의 다른 하나의 뱅크의 대응하는 메모리 셀 플레이트(11, 12; 13, 14; 15, 16; 17, 18)와 나란히 배치되어 상기 뱅크 쌍을 형성하는 것을 특징으로 하는 반도체 메모리 장치.
- 제2항에 있어서, 메인 라인(23) 및 다수의 브랜치 라인(24)을 포함하는 전원선을 더 포함하고, 상기 브랜치 라인(24) 중 하나는 나란히 배치된 한 쌍의 메모리 셀 플레이트(11, 15; 12, 16; 13, 17; 14, 18)에 대해 배치되는 것을 특징으로 하는 반도체 메모리 장치.
- 제2항에 있어서, 상기 메모리 셀 플레이트(11, 12; 13, 14; 15, 16; 17, 18) 각각은 시프트 할당 기술(shift allocation technique)로 배열된 각각의 본딩 패드(31)에 접속된 I/O 단자들을 포함하는 것을 특징으로 하는 반도체 메모리 장치.
- 제1항에 있어서, 상기 메모리 장치는 DDR-SDRAM인 것을 특징으로 하는 반도체 메모리 장치.
- 제1항에 있어서, 상기 I/O 증폭기들(32) 중 적어도 일부는 용장 라인부를 각각 갖는 I/O 버스 라인들(34)과 관련되는 것을 특징으로 하는 반도체 메모리 장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32084799A JP2001143464A (ja) | 1999-11-11 | 1999-11-11 | 半導体記憶装置 |
JP1999-320847 | 1999-11-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010051619A KR20010051619A (ko) | 2001-06-25 |
KR100350590B1 true KR100350590B1 (ko) | 2002-08-29 |
Family
ID=18125919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000066927A KR100350590B1 (ko) | 1999-11-11 | 2000-11-11 | 칩 사이즈가 감소된 dram |
Country Status (4)
Country | Link |
---|---|
US (1) | US6396763B1 (ko) |
JP (1) | JP2001143464A (ko) |
KR (1) | KR100350590B1 (ko) |
TW (1) | TW462128B (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4378015B2 (ja) * | 2000-02-28 | 2009-12-02 | インターナショナル・ビジネス・マシーンズ・コーポレーション | メモリ・チップ |
US7088604B2 (en) * | 2001-03-15 | 2006-08-08 | Micron Technology, Inc. | Multi-bank memory |
US7463267B2 (en) * | 2006-10-26 | 2008-12-09 | Lsi Corporation | System for interleaved storage of video data |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3085241B2 (ja) * | 1997-04-11 | 2000-09-04 | 日本電気株式会社 | 半導体記憶装置 |
KR100266750B1 (ko) * | 1997-11-20 | 2000-09-15 | 윤종용 | 행 프리 챠아지 시간을 줄일 수 있는 고밀도 반도체 메모리 장치 |
JPH11197633A (ja) | 1998-01-06 | 1999-07-27 | Nesutaa:Kk | 廃棄物発酵装置 |
JP4226686B2 (ja) * | 1998-05-07 | 2009-02-18 | 株式会社東芝 | 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ |
JP2000195291A (ja) * | 1998-12-28 | 2000-07-14 | Oki Electric Ind Co Ltd | 半導体記憶装置及びその冗長救済方法 |
-
1999
- 1999-11-11 JP JP32084799A patent/JP2001143464A/ja active Pending
-
2000
- 2000-11-09 US US09/708,656 patent/US6396763B1/en not_active Expired - Lifetime
- 2000-11-10 TW TW089123938A patent/TW462128B/zh not_active IP Right Cessation
- 2000-11-11 KR KR1020000066927A patent/KR100350590B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR20010051619A (ko) | 2001-06-25 |
TW462128B (en) | 2001-11-01 |
JP2001143464A (ja) | 2001-05-25 |
US6396763B1 (en) | 2002-05-28 |
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