KR100336776B1 - Pad forming method for semiconductor device - Google Patents
Pad forming method for semiconductor device Download PDFInfo
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- KR100336776B1 KR100336776B1 KR1019990053456A KR19990053456A KR100336776B1 KR 100336776 B1 KR100336776 B1 KR 100336776B1 KR 1019990053456 A KR1019990053456 A KR 1019990053456A KR 19990053456 A KR19990053456 A KR 19990053456A KR 100336776 B1 KR100336776 B1 KR 100336776B1
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- etching
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000206 photolithography Methods 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 description 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 패드 형성방법에 관한 것으로, 종래 반도체소자의 패드 형성방법은 고온공정 전에 몰리브덴실리사이드로 이루어진 반사방지막을 사진식각공정으로 제거한 후 패시베이션을 형성하고 상기 반사방지막에서 식각한 동일한 부위를 사진식각공정으로 식각하여 패드부분의 금속막이 드러나도록 함으로써 식각이 2단계로 이루어져 공정이 복잡하여 생산성이 떨어지는 문제점이 있었다. 따라서 본 발명은 소자와 연결된 금속배선이 형성된 반도체기판 상에 금속간 절연막을 증착하는 제 1공정과; 상기 금속배선의 일부가 드러나도록 상기 금속간절연막을 식각하고, 그 구조물 상부 전면에 차례로 배리어막, 금속막, 몰리브덴실리사이드의 반사방지막을 형성하고 그 일부를 식각하여 패드를 형성하는 제 2공정과; 상기 형성한 구조물 상부에 차례로 저온산화막, 저온질화막을 형성하는 제 3공정과; 상기 저온질화막, 저온산화막 및 반사방지막을 사진식각공정으로 식각하여 패드가 형성될 부분의 금속막이 드러나도록 하는 제 4공정으로 이루어지는 반도체소자의 패드 형성방법을 통해 반도체소자를 보호하는 패시베이션을 300℃ 이하의 온도에서 증착할 수 있는 저온산화막과 저온 질화막을 이용하여 형성 함으로써 패드를 형성하는 알루미늄과 반사방지막을 형성하는 몰리브덴실리사이드의 열적반응층 형성을 회피할 수 있으므로 패드부분의 금속층을 드러내기위해 상기 패시베이션을 식각하면서 반사방지막까지 한번에 식각하도록 하여 공정을 단순화하고 생산성을 향상시키는 효과가 있다.The present invention relates to a method for forming a pad of a semiconductor device, and the method for forming a pad of a semiconductor device according to the related art removes an antireflection film made of molybdenum silicide by a photolithography process before a high temperature process, forms a passivation, and then removes the same portion of the antireflection film. Etching is performed in two steps by etching the photolithography to expose the metal film of the pad part, which leads to a complicated process and a low productivity. Accordingly, the present invention provides a method for manufacturing a semiconductor device, comprising: a first process of depositing an intermetallic insulating film on a semiconductor substrate on which metal wirings are connected to the device; Etching the intermetallic insulating film so that a part of the metal wiring is exposed, and forming an anti-reflection film of a barrier film, a metal film, and molybdenum silicide in order on the entire upper surface of the structure, and etching a part thereof to form a pad; A third process of sequentially forming a low temperature oxide film and a low temperature nitride film on the formed structure; Passivation for protecting the semiconductor device through the pad forming method of the semiconductor device comprising a fourth step of etching the low-temperature nitride film, the low-temperature oxide film and the anti-reflection film by a photolithography process to reveal the metal film of the portion where the pad is to be formed. By forming using a low temperature oxide film and a low temperature nitride film which can be deposited at a temperature of, it is possible to avoid the thermal reaction layer formation of the aluminum forming the pad and the molybdenum silicide forming the antireflection film, so that the passivation to reveal the metal layer of the pad portion By etching to the anti-reflection film at once, there is an effect to simplify the process and improve the productivity.
Description
본 발명은 반도체소자의 패드 형성방법에 관한 것으로, 특히 몰리브덴실리사이드(MoSi)를 반사방지막으로 사용한 금속배선을 이용하여 패드를 형성하는 공정에 있어서 상기 금속배선 상부에 패시베이션을 형성하고 패드부분을 식각하면서 상기 반사방지막까지 한번에 식각하도록하여 공정을 단순화함으로써 생산성을 향상 시키기에 적당하도록 한 반도체소자의 패드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pad of a semiconductor device. In particular, in the process of forming a pad using a metal wiring using molybdenum silicide (MoSi) as an antireflection film, a passivation is formed on the metal wiring and the pad portion is etched. The present invention relates to a method for forming a pad of a semiconductor device suitable for improving productivity by simplifying a process by etching the antireflection film at once.
종래 반도체소자의 패드 형성방법을 도 1a 내지 도 1e의 수순단면도를 참고하여 설명하면 다음과 같다.A method of forming a pad of a conventional semiconductor device will be described below with reference to the procedure cross-sectional view of FIGS. 1A to 1E.
소자와 연결된 금속배선(2)이 형성된 반도체기판(1) 상에 금속간 절연막(3)을 증착하는 제 1공정과; 상기 금속배선(2)의 일부가 드러나도록 상기 금속간절연막(3)을 식각하고, 그 구조물 상부 전면에 차례로 배리어막(4), 금속막(5), 반사방지막(6)을 형성하고 일부 식각하여 패드를 형성하는 제 2공정과; 상기 패드에서 외부와 연결이 될 금속막(5)부분이 드러나도록 상기 반사방지막(6)의 일부를 사진식각공정으로 식각하는 제 3공정과; 상기 형성한 구조물 상부에 차례로 산화막(7), 질화막(8)을 형성하는 제 4공정과; 상기 질화막(8), 산화막(7)을 사진식각공정으로 식각하여 패드를 드러내는 제 5공정으로 이루어진다.A first step of depositing an intermetallic insulating film 3 on the semiconductor substrate 1 on which metal wirings 2 connected to the device are formed; The intermetallic insulating film 3 is etched so that a part of the metal wiring 2 is exposed, and the barrier film 4, the metal film 5, and the antireflection film 6 are sequentially formed on the entire upper surface of the structure and partially etched. A second step of forming a pad; A third process of etching a portion of the anti-reflection film 6 by a photolithography process so that a portion of the metal film 5 to be connected to the outside is exposed in the pad; A fourth step of sequentially forming an oxide film (7) and a nitride film (8) on the formed structure; The nitride film 8 and the oxide film 7 are etched by a photolithography process to form a pad to expose a pad.
먼저, 도 1a에 도시한 바와 같이 소자와 연결된 금속배선(2)이 형성된 반도체기판(1) 상에 금속간 절연막(3)을 증착한다.First, as shown in FIG. 1A, an intermetallic insulating film 3 is deposited on a semiconductor substrate 1 on which a metal wiring 2 connected to an element is formed.
도 1b에 도시한 바와 같이 상기 금속배선(2)의 일부가 드러나도록 상기 금속간절연막(3)을 식각하고, 그 구조물 상부 전면에 차례로 배리어막(4), 금속막(5), 반사방지막(6)을 형성하고 식각하여 패드를 형성한다.As shown in FIG. 1B, the intermetallic insulating film 3 is etched so that a part of the metal wiring 2 is exposed, and the barrier film 4, the metal film 5, and the antireflection film ( 6) form and etch to form pads.
이때, 상기 배리어막(4)은 몰리브덴실리사이드이고, 상기 금속막(5)은 알루미늄이며 상기 반사방지막(6)은 몰리브덴실리사이드이다.In this case, the barrier film 4 is molybdenum silicide, the metal film 5 is aluminum, and the antireflection film 6 is molybdenum silicide.
도 1c에 도시한 바와 같이 상기 패드에서 외부와 연결이 될 금속막(5)부분이 드러나도록 상기 반사방지막(6)의 일부를 사진식각공정으로 식각한다.As shown in FIG. 1C, a portion of the anti-reflection film 6 is etched by a photolithography process so that a portion of the metal film 5 to be connected to the outside of the pad is exposed.
이때, 상기 반사방지막(6)을 미리 식각하는 이유는 후속공정에서 산화막(7)과 질화막(8)으로 이루어진 패시베이션을 형성하는 공정이 400℃이상이므로 상기 반사방지막(6)을 형성하는 몰리브덴실리사이드와 금속막(5)인 알루미늄이 반응하기 때문이다.In this case, the anti-reflection film 6 is etched in advance because the process of forming a passivation layer consisting of the oxide film 7 and the nitride film 8 in a subsequent process is 400 ° C. or higher, and the molybdenum silicide forming the anti-reflection film 6 and It is because aluminum which is the metal film 5 reacts.
상기 몰리브덴실리사이드와 알루미늄은 300℃ 이상에서 상호 반응하여 그 계면에 열적반응층(MoxSiyAlz)을 형성하며 이는 식각공정에서 제거가 어렵기 때문에 고온공정 전에 미리 식각하여 상기와 같은 문제를 회피한다.The molybdenum silicide and aluminum react with each other at a temperature of 300 ° C. or higher to form a thermal reaction layer (MoxSiyAlz) at an interface thereof, which is difficult to remove in an etching process, so that the molybdenum silicide and aluminum are etched before the high temperature process to avoid the above problems.
도 1d에 도시한 바와 같이 상기 형성한 구조물 상부에 차례로 산화막(7), 질화막(8)을 형성한다.As shown in FIG. 1D, an oxide film 7 and a nitride film 8 are sequentially formed on the formed structure.
이때, 상기 산화막(7), 질화막(8)은 소자를 보호하기위한 패시베이션의 역할을 하게 되는데, 산화막(7)은 PSG(PhosphoSilicate Glass)로 405℃에서 증착되고, 질화막(8)은 440℃ 혹은 285℃에서 증착된다.In this case, the oxide film 7 and the nitride film 8 serve as passivation for protecting the device. The oxide film 7 is deposited at 405 ° C. with PSG (PhosphoSilicate Glass), and the nitride film 8 is 440 ° C. or less. Deposited at 285 ° C.
도 1e에 도시한 바와 같이 상기 질화막(8), 산화막(7)을 사진식각공정으로 식각하여 패드를 드러낸다.As shown in FIG. 1E, the nitride film 8 and the oxide film 7 are etched by a photolithography process to expose a pad.
상기한 바와같은 종래 반도체소자의 패드 형성방법은 고온공정 전에 몰리브덴실리사이드로 이루어진 반사방지막을 사진식각공정으로 제거한 후 패시베이션을 형성하고 상기 반사방지막에서 식각한 동일한 부위를 사진식각공정으로 식각하여 패드부분의 금속막이 드러나도록 함으로써 식각이 2단계로 이루어져 공정이 복잡하여 생산성이 떨어지는 문제점이 있었다.As described above, in the method of forming a pad of a semiconductor device, an antireflection film made of molybdenum silicide is removed by a photolithography process before a high temperature process, and then a passivation is formed, and the same portion etched from the antireflection film is etched by a photolithography process. The etching is performed in two steps by exposing the metal film, which leads to a complexity of the process, thereby reducing productivity.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 몰리브덴실리사이드의 반사방지막과 패시베이션을 한번에 식각하여 패드를 형성하는 금속막이 드러나도록 함으로써 공정을 단순화 하고 생상성을 높일 수 있는 반도체소자의 패드 형성방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to simplify the process and increase productivity by etching the antireflection film and passivation of molybdenum silicide at once to expose the metal film forming the pad. The present invention provides a method for forming a pad of a semiconductor device.
도 1은 종래 반도체소자의 패드 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a method of forming a pad of a conventional semiconductor device.
도 2는 본 발명의 수순단면도.2 is a cross-sectional view of the procedure of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 금속배선21: semiconductor substrate 22: metal wiring
23 : 금속간 절연막 24 : 배리어막23: intermetallic insulating film 24: barrier film
25 : 금속막 26 : 반사방지막25 metal film 26 antireflection film
27 : 저온산화막 28 : 저온질화막27 low temperature oxide film 28 low temperature nitride film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 패드 형성방법은 소자와 연결된 금속배선이 형성된 반도체기판 상에 금속간 절연막을 증착하는 제 1공정과; 상기 금속배선의 일부가 드러나도록 상기 금속간절연막을 식각하고, 그 구조물 상부 전면에 차례로 배리어막, 금속막, 몰리브덴실리사이드의 반사방지막을 형성하고 그 일부를 식각하여 패드를 형성하는 제 2공정과; 상기 형성한 구조물 상부에 차례로 저온산화막, 저온질화막을 형성하는 제 3공정과; 상기 저온질화막, 저온산화막 및 반사방지막을 사진식각공정으로 식각하여 패드가 형성될 부분의 금속막이 드러나도록 하는 제 4공정으로 이루어지는 것을 특징으로 한다.A method of forming a pad of a semiconductor device for achieving the object of the present invention as described above comprises the steps of: depositing an intermetallic insulating film on a semiconductor substrate on which a metal wiring connected to the device is formed; Etching the intermetallic insulating film so that a part of the metal wiring is exposed, and forming an anti-reflection film of a barrier film, a metal film, and molybdenum silicide in order on the entire upper surface of the structure, and etching a part thereof to form a pad; A third process of sequentially forming a low temperature oxide film and a low temperature nitride film on the formed structure; The low-temperature nitride film, the low-temperature oxide film, and the anti-reflection film are etched by a photolithography process, so that a fourth process is performed to expose the metal film on the portion where the pad is to be formed.
상기한 바와 같은 본 발명에의한 반도체소자의 패드 형성방법을 도 2a 내지 도 2d에 도시한 수순단면도를 일 실시예로하여 상세히 설명하면 다음과 같다.A method of forming a pad of a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view of the procedure shown in FIGS. 2A to 2D as an example.
먼저, 도 2a에 도시한 바와같이 소자와 연결된 금속배선(22)이 형성된 반도체기판(21) 상에 금속간 절연막(23)을 증착한다.First, as shown in FIG. 2A, an intermetallic insulating film 23 is deposited on the semiconductor substrate 21 on which the metal wiring 22 connected to the device is formed.
그 다음, 도 2b에 도시한 바와 같이 상기 금속배선(22)의 일부가 드러나도록 상기 금속간절연막(23)을 식각하고, 그 구조물 상부 전면에 차례로 배리어막(24), 금속막(25), 반사방지막(26)을 형성하고, 상기 배리어막(24), 금속막(25), 반사방지막(26)의 일부를 식각하여 패드를 형성한다.Next, as shown in FIG. 2B, the intermetallic insulating film 23 is etched so that a part of the metal wiring 22 is exposed, and the barrier film 24, the metal film 25, An anti-reflection film 26 is formed, and a part of the barrier film 24, the metal film 25, and the anti-reflection film 26 is etched to form a pad.
이때, 상기 배리어막(24)은 몰리브덴실리사이드이고, 상기 금속막(25)은 알루미늄이며 상기 반사방지막(26)은 몰리브덴실리사이드이다.In this case, the barrier layer 24 is molybdenum silicide, the metal layer 25 is aluminum, and the antireflection layer 26 is molybdenum silicide.
그 다음, 도 2c에 도시한 바와 같이 상기 형성한 구조물 상부에 차례로 저온산화막(27), 저온질화막(28)을 형성한다.Next, as illustrated in FIG. 2C, a low temperature oxide film 27 and a low temperature nitride film 28 are sequentially formed on the formed structure.
이때, 상기 반사방지막(6)을 이루는 몰리브덴실리사이드와 금속막(5)을 이루는 알루미늄은 300℃ 이상에서 상호 반응하여 그 계면에 열적반응층(MoxSiyAlz)을 형성하며 이는 식각공정에서 제거가 어렵기 때문에 고온공정이던 패시베이션 형성과정을 저온으로 변경한다.At this time, the molybdenum silicide forming the antireflection film 6 and the aluminum forming the metal film 5 react with each other at 300 ° C. or higher to form a thermal reaction layer (MoxSiyAlz) at the interface, which is difficult to remove during the etching process. Change the passivation process from the high temperature process to low temperature.
상기 저온산화막(27)은 P-Sio로 180℃에서 증착하고, 상기 저온질화막(28)은 285℃의 저온공정을 택해서 증착한다.The low temperature oxide film 27 is deposited by P-Sio at 180 ° C, and the low temperature nitride film 28 is deposited by using a low temperature process of 285 ° C.
그 다음, 도 2d에 도시한 바와 같이 상기 저온질화막(28), 저온산화막(27) 및 반사방지막(26)을 사진식각공정으로 식각하여 패드가 형성될 부분의 금속막(25)이드러나도록 한다.Next, as illustrated in FIG. 2D, the low temperature nitride film 28, the low temperature oxide film 27, and the anti-reflection film 26 are etched by a photolithography process so that the metal film 25 of the portion where the pad is to be formed is formed. .
상기와 같은 저온 패시베이션공정을 이용하여 알루미늄과 몰리브덴실리사이드의 열적반응층 형성을 회피할 수 있다.By using the low temperature passivation process as described above, it is possible to avoid formation of a thermal reaction layer of aluminum and molybdenum silicide.
상기한 바와 같이 본 발명 반도체소자의 패드 형성방법은 반도체소자를 보호하는 패시베이션을 300℃ 이하의 온도에서 증착할 수 있는 저온산화막과 저온 질화막을 이용하여 형성 함으로써 패드를 형성하는 알루미늄과 반사방지막을 형성하는 몰리브덴실리사이드의 열적반응층 형성을 회피할 수 있으므로 패드부분의 금속층을 드러내기위해 상기 패시베이션을 식각하면서 반사방지막까지 한번에 식각하도록 하여 공정을 단순화하고 생산성을 향상시키는 효과가 있다.As described above, the method for forming a pad of the semiconductor device according to the present invention forms a passivation protecting the semiconductor device by using a low temperature oxide film and a low temperature nitride film capable of depositing at a temperature of 300 ° C. or lower, thereby forming an aluminum and an antireflection film. Since the formation of the thermally reactive layer of molybdenum silicide can be avoided, the passivation can be etched at a time while the passivation is etched to reveal the metal layer of the pad portion, thereby simplifying the process and improving productivity.
Claims (2)
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| KR1019990053456A KR100336776B1 (en) | 1999-11-29 | 1999-11-29 | Pad forming method for semiconductor device |
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| KR1019990053456A KR100336776B1 (en) | 1999-11-29 | 1999-11-29 | Pad forming method for semiconductor device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02140955A (en) * | 1988-11-22 | 1990-05-30 | Seiko Epson Corp | Semiconductor device |
| JPH0382032A (en) * | 1989-08-24 | 1991-04-08 | Matsushita Electric Ind Co Ltd | Multilayer wiring structure and manufacture thereof |
| JPH07326672A (en) * | 1994-05-31 | 1995-12-12 | Kawasaki Steel Corp | Forming method of wiring in viahole |
| JPH10303196A (en) * | 1997-04-24 | 1998-11-13 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
| JPH11238732A (en) * | 1998-02-19 | 1999-08-31 | Sony Corp | Wiring structure and formation of bonding pad opening |
-
1999
- 1999-11-29 KR KR1019990053456A patent/KR100336776B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02140955A (en) * | 1988-11-22 | 1990-05-30 | Seiko Epson Corp | Semiconductor device |
| JPH0382032A (en) * | 1989-08-24 | 1991-04-08 | Matsushita Electric Ind Co Ltd | Multilayer wiring structure and manufacture thereof |
| JPH07326672A (en) * | 1994-05-31 | 1995-12-12 | Kawasaki Steel Corp | Forming method of wiring in viahole |
| JPH10303196A (en) * | 1997-04-24 | 1998-11-13 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
| JPH11238732A (en) * | 1998-02-19 | 1999-08-31 | Sony Corp | Wiring structure and formation of bonding pad opening |
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| KR20010048673A (en) | 2001-06-15 |
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