KR100274974B1 - Method for manufacturing metal interconnection of semiconductor device - Google Patents
Method for manufacturing metal interconnection of semiconductor device Download PDFInfo
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- KR100274974B1 KR100274974B1 KR1019980019691A KR19980019691A KR100274974B1 KR 100274974 B1 KR100274974 B1 KR 100274974B1 KR 1019980019691 A KR1019980019691 A KR 1019980019691A KR 19980019691 A KR19980019691 A KR 19980019691A KR 100274974 B1 KR100274974 B1 KR 100274974B1
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- Prior art keywords
- film
- aluminum
- wiring layer
- alumina
- aluminum wiring
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 title claims description 19
- 239000002184 metal Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 title abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 78
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 78
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract 3
- 238000000151 deposition Methods 0.000 claims description 10
- 229910000838 Al alloy Inorganic materials 0.000 claims description 9
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 28
- 238000005260 corrosion Methods 0.000 abstract description 3
- 230000007797 corrosion Effects 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract 2
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 85
- 229910052760 oxygen Inorganic materials 0.000 description 18
- 239000001301 oxygen Substances 0.000 description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 17
- 238000002161 passivation Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 공정에 관한 것으로, 더욱 상세하게는 반도체 소자 제조 공정중 소자와 소자간의 연결선 및 패드 연결을 위한 반도체 소자의 금속 배선층 제조 방법에 관한 것이다.The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a method of manufacturing a metal wiring layer of a semiconductor device for connecting the connection lines and pads between the device and the device during the semiconductor device manufacturing process.
일반적으로 반도체 소자는 개략적으로 반도체 기판에 트랜지스터와 같은 각 개별 소자들을 소자 분리하여 형성한 후 절연막(1)을 증착하고, 패드 연결 또는 분리된 각 소자들을 전기적으로 연결하기 위한 콘택 홀(contact hall)을 형성한 후 알루미늄 또는 알루미늄 합금 등과 같은 금속막을 증착하고 패터닝(patterning)하여 금속 배선층(2)을 형성한 다음, 패시베이션(passivation)막을 증착함으로써 제조한다.In general, a semiconductor device is roughly formed by separating individual elements such as transistors into a semiconductor substrate, depositing an insulating film 1, and contact holes for electrically connecting pads or separated devices. After forming a metal film, such as aluminum or an aluminum alloy, by depositing and patterning (patterning) to form a metal wiring layer (2), it is prepared by depositing a passivation (passivation) film.
이와 같은 반도체 소자의 제조 공정에 있어서, 패터닝된 금속막인 알루미늄 또는 알루미늄 합금 등은 저융점 금속막이므로, 패시베이션막 증착 등과 같은 후속 열 공정에 의해 도 1a 또는 도 1b에서와 같이 힐록(hillock)(3)(4)이 발생하여 소자의 수율을 저하시킨다. 즉, 도 1a와 같이 금속막(2) 상부에 힐록(3)이 발생할 경우에는 후속 평탄화 공정이 어렵게 되거나 다층 배선 공정에서의 접촉성을 저하시키며, 도 1b와 같이 금속막(2)의 측벽에 사이드 힐록(4)이 발생할 경우에는 금속 배선층 사이의 쇼트(short)에 의해 정확한 소자 특성을 얻을 수 없게 된다. 그리고, 금속 배선층 형성 이후 증착되는 패시베이션막이나 다층 배선에서의 층간 절연막 등은 주로 수분을 함유하고 있는 질화막(SiN4) 또는 PSG(phosphosilicate glass)와 같은 산화막 등을 사용하는 데, 이들에 함유된 수분에 의해 도 1c에서와 같이 금속막(2)에 부식된 부분(5)이 발생하여 소자의 특성을 저하시킨다. 또한, 금속 배선층 형성 이후 증착되는 패시베이션막이나 다층 배선에서의 층간 절연막 등에 의한 인장 응력에 의해 금속막(2)이 스트레스를 받아 도 1d에서와 같이 보이드(6)가 발생함으로써 소자의 특성을 저하시킨다.In the manufacturing process of such a semiconductor device, aluminum or aluminum alloy, which is a patterned metal film, is a low melting point metal film, and thus, by a subsequent thermal process such as passivation film deposition or the like, as shown in FIG. 3) (4) occurs to lower the yield of the device. That is, when the hillock 3 occurs on the upper portion of the metal film 2 as shown in FIG. 1A, subsequent planarization processes are difficult or the contactability in the multilayer wiring process is reduced, and as shown in FIG. 1B, the sidewalls of the metal film 2 are formed. When the side heel lock 4 occurs, short device between the metal wiring layers prevents accurate device characteristics from being obtained. The passivation film or the interlayer insulating film in the multilayer wiring, which are deposited after the metal wiring layer is formed, uses an oxide film such as nitride film (SiN 4 ) or phosphosilicate glass (PSG), which mainly contains water, and the moisture contained therein. As a result, as shown in FIG. 1C, the portion 5 which is corroded to the metal film 2 is generated, thereby degrading the characteristics of the device. In addition, the metal film 2 is stressed by the tensile stress caused by the passivation film or the interlayer insulating film in the multilayer wiring after the formation of the metal wiring layer, and the void 6 is generated as shown in FIG. .
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 알루미늄 배선층의 힐록 억제 및 부식 방지가 가능하고, 스트레스의 감소를 가능하게 하는 반도체 소자의 금속 배선층 제조 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a metal wiring layer of a semiconductor device which is capable of suppressing hillock and preventing corrosion of an aluminum wiring layer and reducing stress.
도 1a 내지 도 1d는 종래의 방법에 의해 제조된 알루미늄 배선층에서 발생되는 여러 가지 문제점을 개략적으로 도시한 반도체 기판의 단면도이고,1A to 1D are cross-sectional views of a semiconductor substrate schematically illustrating various problems occurring in an aluminum wiring layer manufactured by a conventional method.
도 2a 내지 도 2c는 본 발명의 제 1실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도이고,2A to 2C are process flowcharts schematically illustrating a method for manufacturing an aluminum wiring layer of a semiconductor device according to a first embodiment of the present invention.
도 3a 내지 도 3c는 본 발명의 제 2실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도이고,3A to 3C are process flowcharts schematically illustrating a method for manufacturing an aluminum wiring layer of a semiconductor device according to a second exemplary embodiment of the present invention.
도 4a 내지 도 4c는 본 발명의 제 3실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도이고,4A to 4C are process flowcharts schematically illustrating a method for manufacturing an aluminum wiring layer of a semiconductor device according to a third exemplary embodiment of the present invention.
도 5a 내지 도 5c는 본 발명의 제 3실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도이다.5A to 5C are process flowcharts schematically illustrating a method for manufacturing an aluminum wiring layer of a semiconductor device according to a third exemplary embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 알루미늄 배선층이 형성된 반도체 기판에 산소원을 플로우시켜 알루미늄 배선층 표면에 알루미나층을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized by forming an alumina layer on the surface of the aluminum wiring layer by flowing an oxygen source to the semiconductor substrate on which the aluminum wiring layer is formed.
상기에서 산소원은 오존으로 하며, 산소원의 플로우시 반도체 기판의 온도를 200℃ 미만이 되도록 유지하는 것이 바람직하다.In the above, the oxygen source is ozone, and it is preferable to maintain the temperature of the semiconductor substrate to be less than 200 ° C during the flow of the oxygen source.
상기 알루미나층의 형성은, 알루미늄막을 증착하고, 패터닝하여 알루미늄 배선층을 형성한 이후, 산소원을 플로우시켜 형성하는 것이 바람직하다.The alumina layer is preferably formed by depositing an aluminum film, patterning the aluminum wiring layer, and then flowing an oxygen source.
또한, 상기 알루미나층의 형성은, 알루미늄막을 증착하고, 산소원을 플로우시켜 알루미늄막 상부 표면에 알루미나층을 형성하고, 패터닝하여 알루미늄 배선층을 형성한 이후, 재차 산소원을 플로우시켜 알루미늄 배선층 양측 표면에 알루미나층을 형성하는 것이 바람직하다.In addition, the alumina layer is formed by depositing an aluminum film, flowing an oxygen source to form an alumina layer on the upper surface of the aluminum film, and patterning to form an aluminum wiring layer, and then again flowing an oxygen source to both surfaces of the aluminum wiring layer. It is preferable to form an alumina layer.
또한, 상기 알루미나층의 형성은, 알루미늄막을 증착하고, 그 상부에 반사방지막을 도포하고 패터닝하여 알루미늄 배선층을 형성한 이후, 산소원을 플로우시켜 알루미나층을 형성하는 것이 바람직하다.In addition, the alumina layer is preferably formed by depositing an aluminum film, applying an antireflection film on the upper portion thereof, and patterning the aluminum layer to form an aluminum wiring layer, and then forming an alumina layer by flowing an oxygen source.
또한, 상기 알루미나층의 형성은, 알루미늄막을 증착하고, 산소원을 플로우시켜 알루미늄막 상부 표면에 알루미나층을 형성하고, 그 상부에 반사방지막을 도포하고 패터닝하여 알루미늄 배선층을 형성한 이후, 재차 산소원을 플로우시켜 알루미나층을 형성하는 것이 바람직하다.In addition, the alumina layer is formed by depositing an aluminum film, flowing an oxygen source to form an alumina layer on the upper surface of the aluminum film, applying an antireflection film on the upper portion thereof, and patterning the aluminum wiring layer. It is preferable to form an alumina layer by flowing.
이하, 첨부된 도면을 참조로 하여 본 발명에 따른 바람직한 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 제 1실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도로, 먼저, 도 2a에서와 같이 반도체 기판(11)에 트랜지스터와 같은 각 개별 소자들을 소자 분리하여 형성한 후, 절연막(12)을 증착한다. 그리고, 패드 연결 또는 분리된 각 소자들을 전기적으로 연결하기 위한 콘택 홀을 형성한 후, 전체 구조상에 알루미늄막(13)을 증착한다. 이때, 금속막으로 알루미늄 합금을 사용할 수도 있다.2A to 2C are process flowcharts schematically showing a method for manufacturing an aluminum wiring layer of a semiconductor device according to a first embodiment of the present invention. First, as shown in FIG. 2A, each individual device such as a transistor is formed on the semiconductor substrate 11. After the isolation is carried out, the insulating film 12 is deposited. Then, after forming contact holes for electrically connecting the pad-connected or separated elements, an aluminum film 13 is deposited on the entire structure. At this time, an aluminum alloy can also be used as a metal film.
그 다음, 반도체 기판(11)의 온도를 약 200℃ 미만이 되도록 유지한 상태에서 산소원 - 산소(O2) 또는 오존(O3), 바람직하게는 오존 - 을 플로우(flow)시켜 알루미늄막(13)의 상부 표면에 알루미나(Al2O3)층(14)을 형성하고, 그 상부에 포토레지스트(photoresist)를 도포한다. 이후, 알루미늄 배선층 패턴을 형성하기 위한 마스크를 통해 포토레지스트를 사진 현상하여 도 2b와 같이 포토레지스트 패턴(PR)을 형성한다.Next, the oxygen source-oxygen (O 2 ) or ozone (O 3 ), preferably ozone-is flowed while the temperature of the semiconductor substrate 11 is maintained to be less than about 200 ° C. An alumina (Al 2 O 3 ) layer 14 is formed on the upper surface of 13), and a photoresist is applied thereon. Thereafter, photoresist is developed through a mask for forming an aluminum wiring layer pattern to form photoresist pattern PR as shown in FIG. 2B.
그 다음, 포토레지스트 패턴(PR)을 마스크로 하여 상부 표면에 알루미나층(14)이 형성된 알루미늄막(13)을 식각하여 알루미늄 배선층 패턴을 형성한다. 이후, 반도체 기판(11)의 온도를 약 200℃ 미만이 되도록 유지한 상태에서 산소원을 플로우시켜 알루미늄 배선층 패턴의 양 측 표면에 알루미나층(15)을 형성하고, 남은 포토레지스트 패턴(PR)을 제거하여 도 2c에서와 같이 상부 표면과 양 측 표면에 알루미나층(14)(15)이 형성된 알루미늄 배선층(13)을 완성한다. 이때, 이와는 달리 포토레지스트 패턴(PR)을 마스크로 하여 상부 표면에 알루미나층(14)이 형성된 알루미늄막(13)을 식각하여 알루미늄 배선층 패턴을 형성하고, 남은 포토레지스트 패턴(PR)을 제거한 다음, 반도체 기판의 온도를 200℃ 미만이 되도록 유지한 상태에서 산소원을 플로우시켜 알루미늄 배선층 패턴의 양 측 표면에 알루미나층(15)을 형성함으로써 도 2c에서와 같이 상부 표면과 양 측 표면에 알루미나층(14)(15)이 형성된 알루미늄 배선층(13)을 완성할 수도 있다.Next, the aluminum layer 13 having the alumina layer 14 formed thereon is etched using the photoresist pattern PR as a mask to form an aluminum wiring layer pattern. Thereafter, the oxygen source is flowed while the temperature of the semiconductor substrate 11 is maintained to be less than about 200 ° C. to form the alumina layers 15 on both surfaces of the aluminum wiring layer pattern, and the remaining photoresist pattern PR is removed. 2C, the aluminum wiring layer 13 having the alumina layers 14 and 15 formed on the upper surface and both surfaces thereof is removed. In this case, the aluminum layer 13 having the alumina layer 14 formed on the upper surface is etched using the photoresist pattern PR as a mask to form an aluminum wiring layer pattern, and the remaining photoresist pattern PR is removed. The alumina layer 15 is formed on both surfaces of the aluminum wiring layer pattern by flowing an oxygen source while maintaining the temperature of the semiconductor substrate to be less than 200 ° C. The aluminum wiring layer 13 in which the 14 and 15 were formed can also be completed.
도 3a 내지 도 3c는 본 발명의 제 2실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도로, 먼저, 도 3a에서와 같이 반도체 기판(11)에 트랜지스터와 같은 각 개별 소자들을 소자 분리하여 형성한 후, 절연막(12)을 증착한다. 그리고, 패드 연결 또는 분리된 각 소자들을 전기적으로 연결하기 위한 콘택 홀을 형성한 후, 전체 구조상에 알루미늄막(13)을 증착한다. 이때, 금속막으로 알루미늄 합금을 사용할 수도 있다.3A to 3C are process flowcharts schematically illustrating a method for manufacturing an aluminum wiring layer of a semiconductor device according to a second embodiment of the present invention. First, as shown in FIG. 3A, each individual device such as a transistor in the semiconductor substrate 11 is illustrated. After the isolation is carried out, the insulating film 12 is deposited. Then, after forming contact holes for electrically connecting the pad-connected or separated elements, an aluminum film 13 is deposited on the entire structure. At this time, an aluminum alloy can also be used as a metal film.
그 다음, 반도체 기판(11)의 온도를 약 200℃ 미만이 되도록 유지한 상태에서 산소원을 플로우시켜 알루미늄막(13)의 상부 표면에 알루미나층(14)을 형성하고, 그 상부에 반사방지막(16)과 포토레지스트를 연속하여 도포한다. 이후, 알루미늄 배선층 패턴을 형성하기 위한 마스크를 통해 포토레지스트를 사진 현상하여 도 3b와 같이 포토레지스트 패턴(PR)을 형성한다.Thereafter, an oxygen source is flowed while the temperature of the semiconductor substrate 11 is maintained to be less than about 200 ° C. to form an alumina layer 14 on the upper surface of the aluminum film 13, and an antireflection film ( 16) and photoresist are applied successively. Thereafter, photoresist is developed through a mask for forming an aluminum wiring layer pattern to form photoresist pattern PR as shown in FIG. 3B.
그 다음, 포토레지스트 패턴(PR)을 마스크로 하여 반사방지막(16)과 상부 표면에 알루미나층이 형성된 알루미늄막(13)을 식각하여 알루미늄 배선층 패턴을 형성한다. 이후, 반도체 기판(11)의 온도를 약 200℃ 미만이 되도록 유지한 상태에서 산소원을 플로우시켜 알루미늄 배선층 패턴의 양 측 표면에 알루미나층(15)을 형성하고, 남은 포토레지스트 패턴(PR)을 제거하여 도 3c에서와 같이 상부 표면과 양 측 표면에 알루미나층(14)(15) 및 상부에 반사방지막(16)이 형성된 알루미늄 배선층(13)을 완성한다. 이때, 이와는 달리 포토레지스트 패턴(PR)을 마스크로 하여 반사방지막(16)과 상부 표면에 알루미나층(14)이 형성된 알루미늄막(13)을 식각하여 알루미늄 배선층 패턴을 형성하고, 남은 포토레지스트 패턴(PR)을 제거한 다음, 반도체 기판의 온도를 200℃ 미만이 되도록 유지한 상태에서 산소원을 플로우시켜 알루미늄 배선층 패턴의 양 측 표면에 알루미나층(15)을 형성함으로써 도 3c에서와 같이 상부 표면과 양 측 표면에 알루미나층(14)(15) 및 상부에 반사방지막(16)이 형성된 알루미늄 배선층(13)을 완성할 수도 있다.Next, the anti-reflection film 16 and the aluminum film 13 having the alumina layer formed on the upper surface thereof are etched using the photoresist pattern PR as a mask to form an aluminum wiring layer pattern. Thereafter, the oxygen source is flowed while the temperature of the semiconductor substrate 11 is maintained to be less than about 200 ° C. to form the alumina layers 15 on both surfaces of the aluminum wiring layer pattern, and the remaining photoresist pattern PR is removed. 3C, the aluminum wiring layer 13 having the alumina layers 14 and 15 and the anti-reflective film 16 formed thereon is formed on the top and both surfaces thereof as shown in FIG. 3C. At this time, unlike this, by using the photoresist pattern PR as a mask, the anti-reflection film 16 and the aluminum film 13 having the alumina layer 14 formed on the upper surface are etched to form an aluminum wiring layer pattern, and the remaining photoresist pattern ( After removing the PR), the oxygen source was flowed while maintaining the temperature of the semiconductor substrate to be less than 200 ° C. to form the alumina layers 15 on both surfaces of the aluminum wiring layer pattern. The aluminum wiring layer 13 in which the alumina layers 14 and 15 and the anti-reflection film 16 were formed on the side surface can also be completed.
도 4a 내지 도 4c는 본 발명의 제 3실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도로, 먼저, 도 4a에서와 같이 반도체 기판(11)에 트랜지스터와 같은 각 개별 소자들을 소자 분리하여 형성한 후, 절연막(12)을 증착한다. 그리고, 패드 연결 또는 분리된 각 소자들을 전기적으로 연결하기 위한 콘택 홀을 형성한 후, 전체 구조상에 알루미늄막(13)을 증착한다. 이때, 금속막으로 알루미늄 합금을 사용할 수도 있다.4A to 4C are process flowcharts schematically showing a method for manufacturing an aluminum wiring layer of a semiconductor device according to a third embodiment of the present invention. First, as shown in FIG. 4A, each individual device such as a transistor in the semiconductor substrate 11 is illustrated. After the isolation is carried out, the insulating film 12 is deposited. Then, after forming contact holes for electrically connecting the pad-connected or separated elements, an aluminum film 13 is deposited on the entire structure. At this time, an aluminum alloy can also be used as a metal film.
그 다음, 알루미늄막(13) 상부에 포토레지스트를 도포하고, 알루미늄 배선층 패턴을 형성하기 위한 마스크를 통해 포토레지스트를 사진 현상하여 포토레지스트 패턴을 형성한다. 그리고, 포토레지스트 패턴을 마스크로 하여 알루미늄막(13)을 식각하고, 남은 포토레지스트 패턴을 제거하여 도 4b에서와 같이 알루미늄 배선층 패턴을 형성한다.Next, a photoresist is applied over the aluminum film 13, and the photoresist is photodeveloped through a mask for forming an aluminum wiring layer pattern to form a photoresist pattern. The aluminum film 13 is etched using the photoresist pattern as a mask, and the remaining photoresist pattern is removed to form an aluminum wiring layer pattern as shown in FIG. 4B.
그 다음, 반도체 기판의 온도를 약 200℃ 미만으로 유지한 상태에서 산소원을 플로우시켜 알루미늄 배선층 패턴의 상부 표면과 양 측 표면에 알루미나층(14)을 형성함으로써 도 4c에서와 같이 상부 표면과 양 측 표면에 알루미나층이 형성된 알루미늄 배선층을 완성한다.Then, the oxygen source was flowed while the temperature of the semiconductor substrate was kept below about 200 ° C. to form the alumina layer 14 on the upper surface and both surfaces of the aluminum wiring layer pattern, thereby increasing the amount of the upper surface and the amount as shown in FIG. The aluminum wiring layer in which the alumina layer was formed in the side surface is completed.
도 5a 내지 도 5c는 본 발명의 제 3실시예에 따른 반도체 소자의 알루미늄 배선층 제조 방법을 개략적으로 도시한 공정 순서도로, 먼저, 도 5a에서와 같이 반도체 기판(11)에 트랜지스터와 같은 각 개별 소자들을 소자 분리하여 형성한 후, 절연막(12)을 증착한다. 그리고, 패드 연결 또는 분리된 각 소자들을 전기적으로 연결하기 위한 콘택 홀을 형성한 후, 전체 구조상에 알루미늄막(13)을 증착한다. 이때, 금속막으로 알루미늄 합금을 사용할 수도 있다.5A to 5C are process flowcharts schematically illustrating a method for manufacturing an aluminum wiring layer of a semiconductor device according to a third embodiment of the present invention. First, as shown in FIG. 5A, each individual device such as a transistor in the semiconductor substrate 11 is illustrated. After the isolation is carried out, the insulating film 12 is deposited. Then, after forming contact holes for electrically connecting the pad-connected or separated elements, an aluminum film 13 is deposited on the entire structure. At this time, an aluminum alloy can also be used as a metal film.
그 다음, 알루미늄막(13) 상부에 반사방지막(16)과 포토레지스트를 연속하여 도포한 후, 알루미늄 배선층 패턴을 형성하기 위한 마스크를 통해 포토레지스트를 사진 현상하여 포토레지스트 패턴을 형성한다. 그리고, 포토레지스트 패턴을 마스크로 하여 반사방지막(16)과 알루미늄막(13)을 식각하고, 남은 포토레지스트 패턴을 제거하여 도 5b에서와 같이 알루미늄 배선층 패턴을 형성한다.Next, after the antireflection film 16 and the photoresist are successively applied on the aluminum film 13, the photoresist is photodeveloped through a mask for forming an aluminum wiring layer pattern to form a photoresist pattern. Then, the antireflection film 16 and the aluminum film 13 are etched using the photoresist pattern as a mask, and the remaining photoresist pattern is removed to form an aluminum wiring layer pattern as shown in FIG. 5B.
그 다음, 반도체 기판의 온도를 약 200℃ 미만이 되도록 유지한 상태에서 산소원을 플로우시켜 알루미늄 배선층 패턴의 양 측 표면에 알루미나층(14)을 형성함으로써 도 5c에서와 같이 상부에는 반사방지막(16)과 양 측 표면에는 알루미나층(14)이 형성된 알루미늄 배선층(13)을 완성한다. 이때, 이와는 달리 포토레지스트 패턴을 마스크로 하여 반사방지막(16)과 알루미늄막(13)을 식각하여 알루미늄 배선층 패턴을 형성하고, 반도체 기판의 온도를 200℃ 미만으로 유지한 상태에서 산소원을 플로우시켜 알루미늄 배선층 패턴의 양 측 표면에 알루미나층(14)을 형성한 후, 남은 포토레지스트 패턴을 제거함으로써 도 5c에서와 같이 상부에는 반사방지막(16)과 양 측 표면에는 알루미나층(14)이 형성된 알루미늄 배선층(13)을 완성한다.Then, an alumina layer 14 is formed on both surfaces of the aluminum wiring layer pattern by flowing an oxygen source while maintaining the temperature of the semiconductor substrate to be less than about 200 ° C., thereby preventing the antireflection film 16 from above. ) And the aluminum wiring layer 13 having the alumina layer 14 formed on both surfaces thereof. At this time, the anti-reflection film 16 and the aluminum film 13 are etched using the photoresist pattern as a mask to form an aluminum wiring layer pattern, and the oxygen source is flowed while maintaining the temperature of the semiconductor substrate below 200 ° C. After forming the alumina layers 14 on both surfaces of the aluminum wiring layer pattern, and removing the remaining photoresist pattern, as shown in Figure 5c the aluminum with the anti-reflection film 16 and the alumina layer 14 formed on both surfaces The wiring layer 13 is completed.
이와 같이 본 발명은 알루미늄 배선층의 표면에 알루미나층을 형성하여 후속 열공정과 패시베이션막 또는 층간절연막의 수분 및 응력에 대한 보호막 역할을 하도록 함으로써 알루미늄 배선층의 힐록 억제 및 부식 방지가 가능하고, 스트레스를 감소시킬 수 있어 반도체 소자의 특성 및 수율을 향상시킬 수 있다.As described above, the present invention forms an alumina layer on the surface of the aluminum wiring layer to serve as a protective film against moisture and stress of the subsequent thermal process and the passivation layer or the interlayer insulating layer, thereby preventing hillock and preventing corrosion of the aluminum wiring layer and reducing stress. It is possible to improve the characteristics and the yield of the semiconductor device.
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| JPH03218631A (en) * | 1990-01-24 | 1991-09-26 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH04164321A (en) * | 1990-10-29 | 1992-06-10 | Nec Corp | Manufacture of semiconductor device |
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| JPH03218631A (en) * | 1990-01-24 | 1991-09-26 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH04164321A (en) * | 1990-10-29 | 1992-06-10 | Nec Corp | Manufacture of semiconductor device |
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