KR19990055192A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR19990055192A KR19990055192A KR1019970075104A KR19970075104A KR19990055192A KR 19990055192 A KR19990055192 A KR 19990055192A KR 1019970075104 A KR1019970075104 A KR 1019970075104A KR 19970075104 A KR19970075104 A KR 19970075104A KR 19990055192 A KR19990055192 A KR 19990055192A
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 비트라인 콘택 저항을 감소시킬 수 있는 반도체 장치 제조 방법에 관한 것으로, 게이트를 이루는 텅스텐 실리사이드막 상에 티타늄 나이트라이드(TiN)막을 증착한 후, 게이트 패턴을 형성함으로써, 게이트와 연결되는 비트라인 패턴을 이루는 폴리실리콘막의 불순물이 외확산 되는 것을 방지하여, 콘택 저항을 감소시켜 소자의 동작 속도를 향상시킬 수 있는 반도체 장치 제조 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device capable of reducing bit line contact resistance, wherein a titanium nitride (TiN) film is deposited on a tungsten silicide layer forming a gate, and then a gate pattern is formed to form a gate pattern. Provided is a method of manufacturing a semiconductor device capable of preventing the diffusion of impurities in a polysilicon film forming a line pattern and reducing contact resistance to improve the operation speed of the device.
Description
본 발명은 반도체 소자의 제조 공정 중 비트라인 콘택 형성 방법에 관한 것이다.The present invention relates to a method for forming a bit line contact during a manufacturing process of a semiconductor device.
반도체 소자의 고집적화로 인하여 콘택홀 크기를 비롯한 패턴 크기의 축소화로 인하여 소자의 동작 속도 지연이 문제가 되고있는데, 이러한 문제를 해결하기 위한 방안으로 256M급 이상의 디램(DRAM) 소자에서는, 종래에 폴리실리콘막으로 형성하던 게이트를 텅스텐 실리사이드로 형성하고 있으나, 이 또한 비트라인(bit line) 콘택의 저항이 높아져 반도체 소자의 불량을 야기시키는 문제가 있었다.Due to the high integration of semiconductor devices, there is a problem in delaying the operation speed of the devices due to the reduction of the pattern size including the contact hole size. In order to solve this problem, in the DRAM devices of 256M or higher, conventionally, Although the gate formed of the film is formed of tungsten silicide, this also has a problem of causing a failure of the semiconductor device due to a high resistance of the bit line contact.
도1a 내지 도1c는 종래 기술에 따른 반도체 장치 제조 공정 단면도이다. 종래 기술에 따른 반도체 장치 제조 방법은 다음과 같이 이루어진다.1A to 1C are cross-sectional views of a semiconductor device manufacturing process according to the prior art. The semiconductor device manufacturing method according to the prior art is made as follows.
먼저, 1A도는 실리콘 기판(11) 상에 게이트 산화막(도시 안됨)과 폴리실리콘막(12) 및 텅스텐 실리사이드막(13)을 차례로 증착한 후, 텅스텐 실리사이드막(13) 상에 반사방지막으로 사용되는 질화막(14)을 증착한 다음, 게이트를 정의하는 감광막 패턴(15)을 형성한다.First, 1A is sequentially deposited a gate oxide film (not shown), a polysilicon film 12 and a tungsten silicide film 13 on the silicon substrate 11, and then used as an antireflection film on the tungsten silicide film 13 After the nitride film 14 is deposited, a photosensitive film pattern 15 defining a gate is formed.
다음으로, 도1b에 도시한 바와 같이 상기 감광막 패턴을(15) 식각마스크로하여 질화막(14), 텅스텐 실리사이드막(13), 폴리실리콘막(12)을 식각하여 게이트 패턴(12', 13' 및 14')을 형성한 후, 감광막 패턴(15)을 제거한 다음, 게이트 패턴(12', 13' 및 14') 측벽에 산화막 스페이서(16)를 형성하고 절연막(17)을 증착한 후, 비트라인 콘택 영역을 정의하는 감광막 패턴(18)을 형성한다.Next, as shown in FIG. 1B, the nitride layer 14, the tungsten silicide layer 13, and the polysilicon layer 12 are etched using the photoresist layer pattern 15 as an etch mask to form gate patterns 12 ′ and 13 ′. And 14 '), and then the photoresist pattern 15 is removed, then oxide film spacers 16 are formed on the sidewalls of the gate patterns 12', 13 'and 14' and the insulating film 17 is deposited. A photoresist pattern 18 defining a line contact region is formed.
다음으로, 도1c에 도시한 바와 같이 감광막 패턴(18)을 식각마스크로하여 절연막(17)을 선택적으로 식각하여 콘택홀을 형성한 후, 감광막 패턴(18)을 제거한다. 이어서, 전체 구조 표면을 따라 폴리실리콘막 및 텅스텐 실리사이드막을 증착하고, 선택적으로 식각하여 비트라인 패턴(19, 20)을 형성한다. 이때, 비트라인의 콘택 저항을 감소시키기 위하여 비트라인 패턴을 이루는 폴리실리콘막(19)에 불순물을 이온주입하는데, 이 경우, " A"와 같이 폴리실리콘막(19)에 주입된 불순물이 게이트 패턴 상부의 텅스텐 실리사이드막(13') 쪽으로 외확산 되어 비트라인 콘택 저항을 높이는 문제점이 존재한다.Next, as shown in FIG. 1C, the insulating film 17 is selectively etched using the photoresist pattern 18 as an etch mask to form a contact hole, and then the photoresist pattern 18 is removed. A polysilicon film and a tungsten silicide film are then deposited along the entire structure surface and selectively etched to form bit line patterns 19 and 20. At this time, in order to reduce the contact resistance of the bit line, impurities are implanted into the polysilicon film 19 forming the bit line pattern. In this case, impurities implanted into the polysilicon film 19 such as "A" are gate patterns. There is a problem of increasing the bit line contact resistance by external diffusion toward the upper tungsten silicide layer 13 '.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 비트라인 콘택 저항을 감소시킬 수 있는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention devised to solve the above problems is to provide a method for manufacturing a semiconductor device that can reduce the bit line contact resistance.
도1a 내지 도1c는 본 발명의 일실시예에 따른 반도체 장치 제조 공정 단면도1A through 1C are cross-sectional views of a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
도2a 내지 도2c는 본 발명의 일실시예에 따른 반도체 장치 제조 공정 단면도2A through 2C are cross-sectional views of a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing
21: 실리콘 기판 22: 폴리실리콘막21: silicon substrate 22: polysilicon film
23: 텅스텐 실리사이드막 24: TiN막23: tungsten silicide film 24: TiN film
25, 28: 감광막 패턴 26: 산화막 스페이서25 and 28 photosensitive film pattern 26 oxide film spacer
27: 절연막 29, 30: 비트라인 패턴27: insulating film 29, 30: bit line pattern
상기 목적을 달성하기 위한 본 발명은 반도체 장치 제조 방법에 있어서, 반도체 기판 상에 제1 전도막 및 TiN막으로 이루어지는 게이트 패턴을 형성하는 단계; 상기 반도체 기판 전면에 절연막을 형성하고 선택적으로 식각하여 상기 TiN막을 노출하는 콘택홀을 형성하는 단계; 및 전체 구조 표면을 따라 폴리실리콘막 및 제2 전도막을 형성하고, 상기 폴리실리콘막 및 제2 전도막을 선택적으로 식각하여 비트라인 패턴을 형성하는 단계를 포함하여 이루어진다.In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a gate pattern including a first conductive film and a TiN film on a semiconductor substrate; Forming a contact hole to expose the TiN film by forming an insulating film on the entire surface of the semiconductor substrate and selectively etching; And forming a polysilicon film and a second conductive film along the entire structure surface, and selectively etching the polysilicon film and the second conductive film to form a bit line pattern.
본 발명은 게이트 패턴을 이루는 텅스텐 실리사이드막 상에 티타늄 나이트라이드(TiN)막을 증착한 후, 게이트 패턴을 형성함으로써, 게이트와 연결되는 비트라인 패턴을 이루는 폴리실리콘막에 주입된 불순물이 외확산되는 것을 방지하여, 콘택 저항을 감소시키는 반도체 장치 제조 방법이다.According to the present invention, a titanium nitride (TiN) film is deposited on a tungsten silicide layer forming a gate pattern, and then a gate pattern is formed, so that impurities injected into the polysilicon layer forming a bit line pattern connected to the gate are externally diffused. It is a semiconductor device manufacturing method which prevents and reduces contact resistance.
도2a 내지 도2c는 본 발명의 일실시예에 따른 반도체 장치 제조 공정 단면도이다. 본 발명의 일실시예에 따른 반도체 장치 제조 방법은 다음과 같이 이루어진다.2A through 2C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention. A semiconductor device manufacturing method according to an embodiment of the present invention is performed as follows.
먼저, 도2a에 도시한 바와 같이 실리콘 기판(21) 상에 게이트 산화막(도시 안됨), 폴리실리콘막(22) 및 텅스텐 실리사이드막(23)을 차례로 증착한 후, 텅스텐 실리사이드막(23) 상에 마스크 작업시 반사방지 및 그 상부에 형성되는 도핑된 실리콘막으로부터의 불순물이 외확산되는 것을 방지하는 TiN막(24)을 100 Å 내지 1000 Å 두께로 증착한 다음, 게이트를 정의하는 감광막 패턴(25)을 형성한다. 상기 텅스텐 실리사이드막(23)을 텅스텐막, 탄탈륨 실리사이드막 또는 티타늄 실리사이드막으로 형성할 수도 있다.First, as shown in FIG. 2A, a gate oxide film (not shown), a polysilicon film 22, and a tungsten silicide film 23 are sequentially deposited on the silicon substrate 21, and then on the tungsten silicide film 23. During the masking operation, a TiN film 24 is deposited to a thickness of 100 to 1000 Å to prevent antireflection and to prevent external diffusion of impurities from the doped silicon film formed thereon, and then a photoresist pattern 25 defining a gate is formed. ). The tungsten silicide film 23 may be formed of a tungsten film, a tantalum silicide film, or a titanium silicide film.
다음으로, 도2b에 도시한 바와 같이 감광막 패턴(25)을 식각마스크로하여 게이트 패턴(22', 23' 및 24')을 형성한 후, 감광막 패턴(25)을 제거한다. 이어서, 게이튼 패턴(22', 23' 및 24') 측벽에 산화막 스페이서(26)를 형성하고, 절연막(27)을 증착한 후, 비트라인 콘택 영역을 정의하는 감광막 패턴(28)을 형성한다.Next, as shown in FIG. 2B, the gate patterns 22 ′, 23 ′, and 24 ′ are formed using the photoresist pattern 25 as an etch mask, and then the photoresist pattern 25 is removed. Subsequently, an oxide spacer 26 is formed on the sidewalls of the gate patterns 22 ', 23', and 24 ', the insulating layer 27 is deposited, and a photosensitive layer pattern 28 defining a bit line contact region is formed. .
상기 산화막 스페이서(26)를 고온산화막(HTO, high temperature oxide), 중온산화막(MTO, medium temperature oxide), 저온산화막(LTO, low temperature oxide) 중의 어느 하나로 형성하거나, 또는 TEOS(tetra ethyl ortho silicate)계 산화막을 저압화학기상증착법 또는 플라즈마화학기상증착법으로 형성한다. 또한, 산화막 스페이서(26)를 실리콘 질화막(SixNx) 또는 실리콘산화질화막[SiOxNy(Hz)]과 같은 질화막으로 형성하기도 한다.The oxide spacer 26 may be formed of any one of a high temperature oxide (HTO), a medium temperature oxide (MTO), and a low temperature oxide (LTO), or tetra ethyl ortho silicate (TEOS). The oxide film is formed by a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method. In addition, the oxide film spacer 26 may be formed of a nitride film such as a silicon nitride film (Si x N x ) or a silicon oxynitride film (SiO x N y (H z )).
상기 절연막(27)을 고온산화막(HTO, high temperature oxide), 중온산화막(MTO, medium temperature oxide), 저온산화막(LTO, low temperature oxide) 중의 어느 하나로 형성하거나, 또는 TEOS(tetra ethyl ortho silicate)계 산화막을 저압화학기상증착법 또는 플라즈마화학기상증착법으로 형성한다. 또한, 상기 절연막(27)을 BPSG막(boro-phosphor silicate glass), PSG(phosphor silicate glass), BSG(boron silicate glass)와 같은 도핑된 산화막으로 형성한다.The insulating layer 27 may be formed of any one of a high temperature oxide (HTO), a medium temperature oxide (MTO), and a low temperature oxide (LTO), or a tetra ethyl ortho silicate (TEOS) system. The oxide film is formed by low pressure chemical vapor deposition or plasma chemical vapor deposition. In addition, the insulating layer 27 is formed of a doped oxide film such as boro-phosphor silicate glass (BPSG), phosphor silicate glass (PSG), or boron silicate glass (BSG).
다음으로 도2C에 도시한 바와 같이 감광막 패턴(28)을 식각마스크로하여 절연막(27)을 선택적으로 식각하여 콘택홀(c2)을 형성한 후, 감광막 패턴(28)을 제거한다. 이어서, 전체 구조 표면을 따라 폴리실리콘막 및 텅스텐 실리사이드막을 증착하고, 선택적으로 식각하여 비트라인 패턴(29, 30)을 형성한다.Next, as shown in FIG. 2C, the insulating layer 27 is selectively etched using the photoresist pattern 28 as an etch mask to form a contact hole c 2 , and then the photoresist pattern 28 is removed. A polysilicon film and a tungsten silicide film are then deposited along the entire structure surface and selectively etched to form bit line patterns 29 and 30.
도면부호 "B"는 상기와 같이 이루어지는 본 발명에서, 비트라인 패턴을 이루는 폴리실리콘막(29)에 주입된 불순물이 게이트 패턴 상부에 형성된 TiN막(24)에 의해 텅스텐 실리사이드막(23)쪽으로 외확산 되지 않음을 나타낸다.In the present invention made as described above, the impurity injected into the polysilicon film 29 forming the bit line pattern is added to the tungsten silicide film 23 by the TiN film 24 formed on the gate pattern. Indicates no diffusion.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어서 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 게이트 패턴으로 사용되는 텅스텐 실리사이드 상부에 TiN막을 증착하여, 추후 형성되는 비트라인 패턴을 이루는 폴리실리콘막의 불순물들이 외확산 되는 것을 방지하여 비트라인 콘택 저항을 감소시킴으로써 소자의 동작 속도를 향상시킬 수 있다.According to the present invention, the TiN film is deposited on the tungsten silicide used as the gate pattern, thereby preventing the impurities from the polysilicon film forming the bit line pattern to be subsequently diffused, thereby reducing the bit line contact resistance. Can improve speed.
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