JPH0382032A - Multilayer wiring structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the reliability of wirings, to inhibit the thinning of the wirings due to irregular reflection from foundation irregularities and to realize the excellent contact of the upper layer wiring and the lower layer wiring by directly connecting the layer of an Al alloy in the lower layer wiring composed of a high melting-point metal or a high melting-point metallic silicide and the Al alloy of the upper layer wiring in an uppermost layer section. CONSTITUTION:The material of an uppermost layer section 13b consists of a high melting-point metal or a high melting-point metallic silicide, laminated wirings in which at least one layer of layers 13a except the uppermost layer section 13b is made up of an Al alloy are used as a lower layer wiring 13, and the Al alloy of an upper layer wiring 18 is connected directly to the layer 13a of the Al alloy in the lower layer wiring 13 in a through-hole 17b bored to an inter-layer insulating film 15 isolating the lower layer wiring 13 and the upper layer wiring 18 composed of the Al alloy. The first laminated wiring 13 using Al-Si 13a as a lower layer and MoSi2 13b as an upper layer is formed, P-SiO2 15 is deposited as the inter-layer insulating film, and a through-hole 17a is bored. MoSi2 13b in the upper layer section of the first laminated wiring 13 is etched, Al-Si 13a is exposed, and Al-Si are deposited, thus shaping the second wiring 18.

Description

[Detailed Description of the Invention] Industrial Application Fields of the Invention The invention relates to a multilayer wiring structure in a semiconductor integrated circuit and its manufacturing method. A cross-sectional view is shown. The manufacturing process of such a multilayer wiring structure will be described below. First, a silicon oxide film (hereinafter abbreviated as BPSG) 52 containing, for example, B and P is formed on a silicon substrate 51 on which semiconductor elements and the like are formed as a first interlayer insulator. Formed as a film
For example, an aluminum alloy containing silicon (hereinafter abbreviated as Al-8i) is formed as the first wiring 53 on the BPSG 52, and then a silicon oxide film (hereinafter abbreviated as p-8iO*) 54 is formed by, for example, a plasma CVD method. A through hole 55 is opened in the p-SiO* 54 by resist etching, which is formed as a second interlayer insulating film and subjected to planarization treatment such as etchback. After performing pretreatment to remove the native oxide film by sputter etching with argon, Al-8i, which will become the upper layer wiring, is deposited to form the second wiring 56 of LAl-8i, forming a two-layer multilayer wiring, but the invention is solved. However, with a simple multilayer wiring structure as shown above (↓
As design rules become finer with the aim of improving the degree of integration of semiconductor integrated circuits, the following problems have arisen that cannot be addressed (1. :Top As the wiring width becomes finer, the reliability of the wiring decreases due to stress migration and electromigration, but the reflectance of Al-3i is high.Photoresist pattern formation for forming wiring patterns The photoresist pattern becomes thinner due to unnecessary reflection of exposure light due to the unevenness of the underlying layer, making it difficult to form a uniform pattern.Especially in a multilayer wiring structure, since the tit and the lower layer wiring side are finer, these effects become more pronounced. In order to improve these problems, for JQ 1, there is a method of using a layered wiring of a high melting point metal or a high melting point metal silicide and an Al alloy for the lower layer wiring, and for 2, there is a method of using an anti-reflection film on the Al alloy layer. Even if it is considered to provide a layer with If a through hole is opened in the lower layer wiring and the refractory metal or refractory metal silicide in the upper layer is directly connected to the Al alloy in the upper layer wiring, silicon will precipitate in the through hole and the contact resistance will increase. The present invention has been developed in view of the problem of poor support through holes, which improves the reliability of wiring, suppresses thinning of wiring due to diffused reflection from uneven underlying layers, and improves wiring reliability. It is an object of the present invention to provide a multilayer wiring structure that can realize good contact between lower layer wiring and a method for manufacturing the same.The present invention is intended to solve the above problems. A laminated wiring made of a gold layer or a high melting point metal silicide, and at least one of the layers other than the uppermost layer is made of an Al alloy is used as a lower layer wiring, and an interlayer insulating film is used to separate the lower layer wiring and the upper layer wiring made of an Al alloy. The present invention provides a multilayer wiring structure characterized in that the Al alloy of the upper layer wiring is directly connected to the Al alloy layer of the lower wiring in the opened through hole. Depending on the structure, the high-melting point metal or high-melting point metal silicide used as the laminated wiring has a high resistance to stress migration and electromigration.
The reliability of wiring is improved, and the use of high-melting point metals or high-melting point metal silicides as materials for the upper layer of laminated wiring reduces reflectance, which can be used when forming photoresist patterns to form wiring patterns. It is also possible to suppress thinning of the photoresist pattern due to unnecessary reflection of exposure light due to the unevenness of the underlying surface. The cause is that excess Si in the Al alloy preferentially precipitates on the high melting point metal or high melting point metal silicide exposed through the through hole, and the high contact resistance is due to the connection between dissimilar materials. In order to prevent these problems, we use a connection IQ between the first layer wiring and the lower layer wiring in the through hole.By using a configuration in which the connection is made of Al alloy, which is a common material for the upper and lower layer wiring, defects due to silicon precipitation in the through hole area can be avoided. Embodiment (Example 1) A first embodiment of the present invention will be explained with reference to FIG. 1st on top
A I-8i 13 is formed as a conductor film for the lower wiring where BPSG12 is formed as an interlayer film.
a and a high melting point metal or high melting point metal silicide (hereinafter referred to as
For simplicity, M o S is used as a layer of high melting point metal, etc.)
After that, a photoresist 14 of a shoe wiring pattern is formed (FIG. 1(a)). At this time, the photoresist 1 for forming the wiring pattern is
The reflectance of Mo5ia13b during exposure for 4-form
Al-3i 13a is smaller than I-3i 13a. Fine patterns can be formed by preventing thinning of the photoresist pattern due to diffuse reflection of exposure light due to unevenness of the underlying surface. To form the first laminated wiring 13 with the MoSi layer 13b as the lower layer and the MoSi layer 13b as the upper layer, a p-SiO layer 15 is deposited as an interlayer insulating film, planarized by an etch-back method, etc., and a through-hole pattern is photocoated. A resist 16 is formed (FIG. 1(b)). Next is an example l;! Using the photoresist 16 as a mask, the p-3iOe 15 is etched by dry etching using a mixed gas of CHF and Oe to open the through hole 17a (FIG. 1(e)).
For example, using a mixed gas of CF4 and 02, and using the photoresist 16 as a mask,
o5is13b is etched and a through hole 17b reaching Al-3i13a is opened LA Al-3i1
3a is exposed (FIG. 1(d)). At this time, M.

Si*13b is etched b<, Al-8i13
The resistive photoresist 16 is removed and AlSi is deposited as the upper layer wiring. Before this deposition, for example, sputter etching is performed using argon to expose the first laminated wiring through the through hole 17b. It is desirable to remove the natural oxide film on the surface of the Al-5i 13a of No. 13, t,%. This processing machine deposits Al-5i, which will become the upper layer wiring, and forms a pattern to form the second wiring 18 (see Fig. 1). (e)). This makes it possible to form the multilayer wiring structure of the present invention.
t p -8i Mixture of CHF* and O book for etching of Omaro15, CF for etching of LMoSi213b
Using a mixed gas of a and 02, p-3iO* and Mo
Only a mixed gas of fAcF4 and O2 is used to etch Si* separately. You can also etch p-3ins and MoSi at the same time. Chickens that can be etched using the same method (Example 2) Next, the second example of the present invention will be explained. Since it is the same as the example, we will explain it using Figure 1.
) up to the state shown.

It can be carried out in exactly the same way as in the first embodiment, that is, in the first embodiment of the board.
o S i Etching is performed at position 13b (FIG. 1(d)), but in the second embodiment g! First laminated wiring 1
What is the state of the through hole 17a after etching only the interlayer insulating film (FIG. 1(C))? When the photoresist 16 is removed, the high-melting point metal, etc. is exposed in the through-hole of the plate, and the Al alloy is not exposed.Next, before depositing Al-5i, which will become the upper layer wiring, the through-hole 17a is exposed.
M o S of the upper layer part of the first laminated wiring 13 exposed by
i The pattern 13b is etched away by argon sputter etching to form a through hole 17b that reaches the Al-5i 13a and exposes the LA Al-3i 13a (FIG. 1(f)). This resistor continues with Al, which becomes the upper layer wiring.
-3i is deposited and patterned to form the second wiring 18 (FIG. 1(e)). This allows the formation of the multilayer wiring structure of the present invention. (in this example, p-8i0215) is easily sputtered, and a small surface is formed here, which has the effect of improving the coverage of the upper layer wiring. High-melting point metals, etc. (A I-8i and Mo5ie in the first embodiment) are exposed in the through holes.Cleaning after resist removal, etc.
Force 1 that may cause corrosion of AI alloy and high melting point metal etc. due to battery effect etc. In this example, when opening a through hole, high melting point metal etc. (in this example Mo Si *13)
Since only b) is exposed, such corrosion does not occur (Example 3) Next, a third example of the present invention will be explained with reference to FIG. Where the BPSG 32 is formed as the first interlayer film on the silicon substrate 31, Al-5i 33a is deposited under Ni as in the first embodiment.
After forming the first laminated wiring 33 with l M o S i *33b as the upper layer, 811
A photoresist 34 having an opening larger than the diameter of the through hole to be opened is formed (FIG. 2(a)). The opening of the photoresist 34 formed at this time (↓ It should be formed to a size that does not protrude from the first laminated wiring 33. The opening of the photoresist 34 to be formed at this time should be 1.1 to 1.1 mm of the diameter of the through hole, taking into account misalignment during photoresist formation. Even if .5 times is appropriate, next, for example, C
1. Using a mixed gas of F4 and Os and using the photoresist 34 as a mask. Mo of the upper layer of the first laminated wiring 33
Etching S i *33b L Al-5i33a
A MoSi* removal region 35 is formed, which is a region from which a high melting point metal or the like is removed (FIG. 2(b)). At this time, M
o5t elephant 33b is etched force <, Al-3i3
3a is a chicken that is not etched by fluorine gas.
Remove the photoresist 34 and use p-5 as an interlayer insulating film.
Deposit the iO layer 36 and planarize it using an etch-back method or the like to form a photoresist 3 with a through-hole pattern.
7 (Fig. 2(C)). Next, example haCHF5
Using the photoresist 37 as a mask, p-8iO2 36 is etched by dry etching with a mixed gas of
Figure 2 (d>). Before removing the photoresist 37 and depositing Al-3i, which will become the upper layer wiring, sputter etching is performed using argon, for example, on the MoSi* removed region 35 of the first laminated wiring 33 exposed through the through hole 38. It is desirable to remove the natural oxide film on the surface of the Al-8i 33a. Using this processing machine, Al-8t, which will become the upper layer wiring, is deposited and patterned to form the second wiring 38 (FIG. 2(e)). As a result, the multilayer wiring structure of the present invention can be formed. Normally, after forming the lower layer wiring, sintering is performed to ensure contact between the upper and lower layer wiring and the silicon substrate. However, in this example, there may be a case where a reaction occurs between the high melting point metal, etc. and the Al alloy (MoSix and Al-5i in these examples), making it difficult to remove the high melting point metal, etc. However, in this example, (upper and lower layer wiring) After formation and before sintering, high melting point metal etc. (MoSix in this example)
The problem of removing high melting point metals, etc. can be avoided by removing
Also, due to the through-hole opening, the first embodiment
The Al alloy and high melting point metal, etc. (Al alloy and MoSi in these examples) are exposed in the through hole. In this example, only the Al alloy is exposed in the through hole. In addition, in the second example as well, corrosion may occur locally in the high melting point metal etc. in the through hole. If there is a pinhole or the like, corrosion as described above may occur. In this example, such a problem may not occur (Example 4) Next, a fourth example of the present invention The manufacturing process of the fourth embodiment (the upper and lower wiring formation steps are different, but the steps after the interlayer insulating film formation step are the same as those of the third embodiment, so we will explain it using FIG. 2). BPS is deposited as a first interlayer film on the silicon substrate 31 on which the semiconductor element is formed.
Where G32 is formed, A I-3i 33a and MoSi e3 are used as the multilayer film of the lower wiring.
After depositing the photoresist 3b, a photoresist 34 having an opening larger than the diameter of the through hole to be opened is formed in the area where the through hole is to be connected to the upper layer wiring (FIG. 2(f)). Next, use a mixed gas of, for example, CFa and 02. Using the photoresist 34 as a mask, remove the MoSi * 33b on the upper layer of the multilayer film by etching to expose the Al-3i 33a and remove the high melting point metal etc. M becomes.

A Sit removal region 35 is formed (FIG. 2(g)). At this time, MoSi*33b has an etching force <, Al
-3i33a is a chicken that is not etched by fluorine gas.
This resistor photoresist 34 is removed and a photoresist 40 for forming lower layer wiring is formed (FIG. 2(h)), A.
The first laminated interconnection 33 with L-8i 33a as the lower layer and MoSi*33b as the upper layer is formed by dry etching.
Since this part corresponds to a non-exposed part, it does not affect the effect of preventing unnecessary diffuse reflection of exposure light, as in the first to third embodiments. L~ The multilayer wiring structure of the present invention can be formed by performing the steps shown in FIGS. 2(C) to 2(e) in the same manner as in the third embodiment. Although the effects described in the third embodiment were obtained in exactly the same way, in the third embodiment, the opening protruded from the first laminated wiring 33 when forming the photoresist 34 that forms the region from which high-melting point metals, etc. are removed. (In this example, the insulating film under the first laminated wiring (B
However, in this embodiment, since the high melting point metal, etc. is removed before wiring formation, it is necessary to prevent the PSG32) from protruding from the wiring formation area. In the first to fourth embodiments described above, the strength of the 4L layer using Al-3i and MoSi* laminated wiring as the lower layer wiring does not occur. For example, if 4iAI alloy contains copper, titanium, etc. in addition to silicon, α Sunawa &
Al-3i-Cu, Al-8t-Ti, Al-3i-
Even Cu-Ti etc. 1 Especially Tt.

AI alloy containing Cu has the effect of improving electromigration, stress migration, etc. Also, as a high melting point metal or high melting point metal silicide, in addition to aMosi, W, Ti, Mo,
Ni, Tie, TiN, WSi2, TiSi elephant, Ta
It is also possible to use 5is, CoSi, NiSi2, PtSi, etc. Also, in the first to fourth embodiments described above, contact to the silicon substrate is formed using two-layer laminated wiring. Tagame: You can use barrier metal for this contact to form a laminated wiring of three or more layers.b If you do this, you can also form a good contact to the silicon substrate, but also on the Al alloy layer of the lower wiring. In the above embodiments, the layer C is made of a high melting point metal or a high melting point metal silicide.
Two or more layers may be used. Also, as an interlayer insulating film between the upper layer wiring and the lower layer wiring (using Lp-8iO2 and using the etch-back method as the planarization method), use an organic film such as #tSOG or polyimide by coating. Effects of the Invention As is clear from the above explanation, according to the present invention, by using a laminated wiring containing a high-melting point metal or a high-melting point metal silicide, it is possible to form an interlayer planar film by flattening the layer. Although it is possible to obtain a multilayer wiring structure that is resistant to migration and electromigration and has high reliability, it is also possible to obtain a structure in which connections are made using Al alloy, which is a common material for upper and lower layer wiring. By using high melting point metal or high melting point metal silicide for the upper layer material of the laminated wiring, it is possible to prevent defects due to silicon precipitation in the through hole part and form a stable contact with low resistance. When forming a photoresist pattern to form a wiring pattern, it is possible to suppress thinning of the photoresist pattern due to unnecessary reflection of exposure light due to unevenness of the underlying surface. The process margin of photolithography is large, which makes it possible to form highly integrated and highly reliable multilayer wiring structures.

[Brief explanation of drawings]

FIG. 1 shows the first embodiment of the present invention. FIG. 2 is a process cross-section showing the method for manufacturing a multilayer wiring structure in the second embodiment. Figure 3 is a cross-sectional view of a multilayer wiring structure according to a conventional technique.
．． 33...First laminated IL 18.39...Second IL
15.36- p-3i O elephant.

Claims (5)

[Claims] (1) A laminated wiring in which the material of the uppermost layer is made of a high melting point metal or a high melting point metal silicide, and at least one of the layers other than the uppermost layer is made of an Al alloy is used as the lower wiring, and the lower wiring and the Al alloy A multilayer wiring structure characterized in that the Al alloy of the upper layer wiring is directly connected to the Al alloy layer of the lower layer wiring in a through hole opened in an interlayer insulating film separating the upper layer wiring made of structure. (2) forming a lower layer wiring having a laminated structure in which the uppermost layer is made of a high melting point metal or high melting point metal silicide and at least one layer other than the uppermost layer is made of an Al alloy; forming an interlayer insulating film on the interlayer insulating film; forming a photoresist to form a through hole on the interlayer insulating film; etching the interlayer insulating film to open the through hole; A step of etching away the uppermost layer of the lower layer wiring exposed by the through hole to a layer above the Al alloy layer as a mask to expose the Al alloy layer, and a step of removing the upper layer wiring made of the Al alloy after removing the photoresist. A method for forming a multilayer wiring, comprising a step of forming a multilayer wiring. (3) forming a lower layer wiring having a laminated structure in which the uppermost layer is made of a high melting point metal or high melting point metal silicide, and at least one layer other than the uppermost layer is made of an Al alloy; and the lower layer wiring forming an interlayer insulating film on the interlayer insulating film; forming a photoresist to form a through hole on the interlayer insulating film; etching the interlayer insulating film to open the through hole; and removing the photoresist. After that, before depositing the Al alloy film that will become the upper layer wiring, argon sputter etching is performed to remove the uppermost layer of the lower layer wiring exposed by the through hole to the layer above the Al alloy layer to expose the Al alloy layer. A method for forming a multilayer interconnection comprising the steps of: and forming an upper layer interconnection made of the Al alloy. (4) forming a lower layer wiring having a laminated structure in which the uppermost layer is made of a high melting point metal or high melting point metal silicide and at least one layer other than the uppermost layer is made of an Al alloy; A photoresist having an exposed portion larger than the diameter of the through hole is formed at the portion where the upper through hole is to be connected to the upper layer wiring, and using the photoresist as a mask, the uppermost layer of the lower layer wiring is connected to the top layer of the Al alloy layer. forming a high melting point metal or high melting point metal silicide removal region to expose the Al alloy layer, and forming an interlayer insulating film on the lower wiring after removing the photoresist. , a process of forming a photoresist for forming a through hole and opening a through hole in the interlayer insulating film; and a process of forming an upper layer wiring made of an Al alloy after removing the photoresist. Formation method. (5) A multilayer film serving as a material for forming a lower layer wiring having a laminated structure in which the uppermost layer is made of a high-melting point metal or a high-melting point metal silicide, and at least one layer other than the above-mentioned uppermost layer is made of an Al alloy. a step of forming a photoresist having an exposed portion larger than the diameter of the through hole for a portion of the multilayer film that is to be connected to the upper layer wiring through the through hole; A from the top layer of the multilayer film using the resist as a mask
A step of removing up to the upper layer of the Al alloy layer and forming a high melting point metal or high melting point metal silicide removal region to expose the Al alloy layer, and processing the multilayer film into a lower wiring after removing the photoresist. a step of forming an interlayer insulating film on the lower wiring; a step of forming a photoresist for forming the through hole; and a step of opening a through hole in the interlayer insulating film; and after removing the photoresist. A method for forming a multilayer wiring comprising the step of forming an upper layer wiring made of an Al alloy.