KR100311886B1 - 실리콘-온-절연체기판의 표면실리콘층의두께를변화시키기위한방법 - Google Patents

실리콘-온-절연체기판의 표면실리콘층의두께를변화시키기위한방법 Download PDF

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Publication number
KR100311886B1
KR100311886B1 KR1019940014414A KR19940014414A KR100311886B1 KR 100311886 B1 KR100311886 B1 KR 100311886B1 KR 1019940014414 A KR1019940014414 A KR 1019940014414A KR 19940014414 A KR19940014414 A KR 19940014414A KR 100311886 B1 KR100311886 B1 KR 100311886B1
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South Korea
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layer
silicon
substrate
shielding
shielding layer
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KR1019940014414A
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KR950001884A (ko
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케이스에이.조이너
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윌리엄 비. 켐플러
텍사스 인스트루먼츠 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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  • Element Separation (AREA)
KR1019940014414A 1993-06-24 1994-06-23 실리콘-온-절연체기판의 표면실리콘층의두께를변화시키기위한방법 Expired - Lifetime KR100311886B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/082,080 US5364800A (en) 1993-06-24 1993-06-24 Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate
US08/082.080 1993-06-24

Publications (2)

Publication Number Publication Date
KR950001884A KR950001884A (ko) 1995-01-04
KR100311886B1 true KR100311886B1 (ko) 2002-04-24

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KR1019940014414A Expired - Lifetime KR100311886B1 (ko) 1993-06-24 1994-06-23 실리콘-온-절연체기판의 표면실리콘층의두께를변화시키기위한방법

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US (2) US5364800A (enExample)
EP (1) EP0658930A3 (enExample)
JP (1) JPH07142567A (enExample)
KR (1) KR100311886B1 (enExample)
TW (1) TW267248B (enExample)

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US6572925B2 (en) 2001-02-23 2003-06-03 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material
US6649219B2 (en) 2001-02-23 2003-11-18 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
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US6503840B2 (en) 2001-05-02 2003-01-07 Lsi Logic Corporation Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
US6559048B1 (en) 2001-05-30 2003-05-06 Lsi Logic Corporation Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
US6583026B1 (en) 2001-05-31 2003-06-24 Lsi Logic Corporation Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure
US6562700B1 (en) 2001-05-31 2003-05-13 Lsi Logic Corporation Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal
US6566171B1 (en) 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
US6930056B1 (en) 2001-06-19 2005-08-16 Lsi Logic Corporation Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure
US6559033B1 (en) 2001-06-27 2003-05-06 Lsi Logic Corporation Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6673721B1 (en) 2001-07-02 2004-01-06 Lsi Logic Corporation Process for removal of photoresist mask used for making vias in low k carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask
US6723653B1 (en) 2001-08-17 2004-04-20 Lsi Logic Corporation Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material
US6881664B2 (en) * 2001-08-28 2005-04-19 Lsi Logic Corporation Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
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US7115463B2 (en) * 2004-08-20 2006-10-03 International Business Machines Corporation Patterning SOI with silicon mask to create box at different depths
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Also Published As

Publication number Publication date
KR950001884A (ko) 1995-01-04
US5364800A (en) 1994-11-15
TW267248B (enExample) 1996-01-01
EP0658930A2 (en) 1995-06-21
JPH07142567A (ja) 1995-06-02
US5548149A (en) 1996-08-20
EP0658930A3 (en) 1997-10-01

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