KR100285823B1 - 디램 셀 장치 - Google Patents

디램 셀 장치 Download PDF

Info

Publication number
KR100285823B1
KR100285823B1 KR1019950700490A KR19950700490A KR100285823B1 KR 100285823 B1 KR100285823 B1 KR 100285823B1 KR 1019950700490 A KR1019950700490 A KR 1019950700490A KR 19950700490 A KR19950700490 A KR 19950700490A KR 100285823 B1 KR100285823 B1 KR 100285823B1
Authority
KR
South Korea
Prior art keywords
bit line
region
transistors
adjacent
along
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019950700490A
Other languages
English (en)
Korean (ko)
Other versions
KR950703208A (ko
Inventor
볼프강 뢰즈너
Original Assignee
칼 하인쯔 호르닝어
지멘스 악티엔게젤샤프트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 칼 하인쯔 호르닝어, 지멘스 악티엔게젤샤프트 filed Critical 칼 하인쯔 호르닝어
Publication of KR950703208A publication Critical patent/KR950703208A/ko
Application granted granted Critical
Publication of KR100285823B1 publication Critical patent/KR100285823B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905—Plural dram cells share common contact or common trench
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/908—Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
KR1019950700490A 1992-08-10 1993-06-23 디램 셀 장치 Expired - Fee Related KR100285823B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4226454 1992-08-10
DEP4226454.5 1992-08-10
PCT/DE1993/000542 WO1994003898A1 (de) 1992-08-10 1993-06-23 Dram-zellenanordnung

Publications (2)

Publication Number Publication Date
KR950703208A KR950703208A (ko) 1995-08-23
KR100285823B1 true KR100285823B1 (ko) 2001-04-16

Family

ID=6465239

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950700490A Expired - Fee Related KR100285823B1 (ko) 1992-08-10 1993-06-23 디램 셀 장치

Country Status (9)

Country Link
US (1) US5600162A (https=)
EP (1) EP0654166B1 (https=)
JP (1) JPH07509808A (https=)
KR (1) KR100285823B1 (https=)
AT (1) ATE137048T1 (https=)
DE (1) DE59302290D1 (https=)
HK (1) HK1001179A1 (https=)
TW (1) TW228594B (https=)
WO (1) WO1994003898A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821592A (en) * 1997-06-30 1998-10-13 Siemens Aktiengesellschaft Dynamic random access memory arrays and methods therefor
US6455886B1 (en) 2000-08-10 2002-09-24 International Business Machines Corporation Structure and process for compact cell area in a stacked capacitor cell array
US6545935B1 (en) 2000-08-29 2003-04-08 Ibm Corporation Dual-port DRAM architecture system
US6831320B2 (en) * 2002-09-30 2004-12-14 Infineon Technologies Ag Memory cell configuration for a DRAM memory with a contact bit terminal for two trench capacitors of different rows
JP4413536B2 (ja) * 2003-06-23 2010-02-10 株式会社東芝 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2590171B2 (ja) * 1988-01-08 1997-03-12 株式会社日立製作所 半導体記憶装置
US5235199A (en) * 1988-03-25 1993-08-10 Kabushiki Kaisha Toshiba Semiconductor memory with pad electrode and bit line under stacked capacitor
US5091761A (en) * 1988-08-22 1992-02-25 Hitachi, Ltd. Semiconductor device having an arrangement of IGFETs and capacitors stacked thereover
JPH0279463A (ja) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp 半導体記憶装置
JPH0294471A (ja) * 1988-09-30 1990-04-05 Toshiba Corp 半導体記憶装置およびその製造方法
JP2528731B2 (ja) * 1990-01-26 1996-08-28 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2818964B2 (ja) * 1990-03-30 1998-10-30 三菱電機株式会社 積層構造の電荷蓄積部を有する半導体記憶装置の製造方法
KR930007194B1 (ko) * 1990-08-14 1993-07-31 삼성전자 주식회사 반도체 장치 및 그 제조방법

Also Published As

Publication number Publication date
DE59302290D1 (de) 1996-05-23
ATE137048T1 (de) 1996-05-15
US5600162A (en) 1997-02-04
TW228594B (https=) 1994-08-21
JPH07509808A (ja) 1995-10-26
WO1994003898A1 (de) 1994-02-17
HK1001179A1 (en) 1998-05-29
EP0654166B1 (de) 1996-04-17
KR950703208A (ko) 1995-08-23
EP0654166A1 (de) 1995-05-24

Similar Documents

Publication Publication Date Title
KR100793932B1 (ko) 메모리 셀 어레이
US5977580A (en) Memory device and fabrication method thereof
US5281837A (en) Semiconductor memory device having cross-point DRAM cell structure
US5032882A (en) Semiconductor device having trench type structure
EP0475280B1 (en) Semiconductor memory device
KR930010823B1 (ko) 반도체 기억장치
US6300654B1 (en) Structure of a stacked memory cell, in particular a ferroelectric cell
KR970030855A (ko) 반도체 메모리 장치 및 그의 제조방법
US7282761B2 (en) Semiconductor memory devices having offset transistors and methods of fabricating the same
US4131906A (en) Dynamic random access memory using MOS FETs and method for manufacturing same
KR0176716B1 (ko) 반도체메모리장치 및 그 제조방법
US5229314A (en) Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation
KR100190522B1 (ko) 반도체 메모리 집적회로 및 그 제조방법
KR0140044B1 (ko) 메모리 셀중에 절연 구조를 가지는 반도체 메모리 소자
KR940010833B1 (ko) 다이나믹형 반도체메모리
US6872996B2 (en) Method of fabricating a ferroelectric stacked memory cell
KR100285823B1 (ko) 디램 셀 장치
JP3905713B2 (ja) メモリセル領域を備えた半導体メモリ
KR100260560B1 (ko) 실리콘-온 인슐레이터 구조를 이용한 반도체 메모리 장치 및 그제조 방법
KR960012495A (ko) 메모리 셀용 스위칭 트랜지스터 및 캐패시터
HK1001179B (en) Dram cell assembly
JPS63110666A (ja) ダイナミック半導体メモリ用メモリセル装置とその製法
US4173819A (en) Method of manufacturing a dynamic random access memory using MOS FETS
JPH0982904A (ja) ダイナミック型メモリ及びその製造方法
JP2554332B2 (ja) １トランジスタ型ダイナミツクメモリセル

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20090105

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20100109

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20100109

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000