KR100280167B1 - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR100280167B1
KR100280167B1 KR1019980045062A KR19980045062A KR100280167B1 KR 100280167 B1 KR100280167 B1 KR 100280167B1 KR 1019980045062 A KR1019980045062 A KR 1019980045062A KR 19980045062 A KR19980045062 A KR 19980045062A KR 100280167 B1 KR100280167 B1 KR 100280167B1
Authority
KR
South Korea
Prior art keywords
contact
mis transistor
gate
conductive
cap layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980045062A
Other languages
English (en)
Korean (ko)
Other versions
KR19990037416A (ko
Inventor
가즈마사 스노우치
Original Assignee
니시무로 타이죠
가부시끼가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 니시무로 타이죠, 가부시끼가이샤 도시바 filed Critical 니시무로 타이죠
Publication of KR19990037416A publication Critical patent/KR19990037416A/ko
Application granted granted Critical
Publication of KR100280167B1 publication Critical patent/KR100280167B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
KR1019980045062A 1997-10-28 1998-10-27 반도체장치 및 그 제조방법 Expired - Fee Related KR100280167B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9295420A JPH11135779A (ja) 1997-10-28 1997-10-28 半導体装置及びその製造方法
JP97-295420 1997-10-28

Publications (2)

Publication Number Publication Date
KR19990037416A KR19990037416A (ko) 1999-05-25
KR100280167B1 true KR100280167B1 (ko) 2001-02-01

Family

ID=17820383

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980045062A Expired - Fee Related KR100280167B1 (ko) 1997-10-28 1998-10-27 반도체장치 및 그 제조방법

Country Status (4)

Country Link
US (1) US6300178B1 (enExample)
JP (1) JPH11135779A (enExample)
KR (1) KR100280167B1 (enExample)
TW (1) TW402818B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387759B1 (en) * 1998-05-18 2002-05-14 Hyundai Electronics Industries Co., Ltd. Method of fabricating a semiconductor device
KR100328810B1 (ko) * 1999-07-08 2002-03-14 윤종용 반도체 장치를 위한 콘택 구조 및 제조 방법
US6399470B1 (en) * 2000-10-05 2002-06-04 Oki Electronic Industry Co., Ltd. Method for forming contact holes on conductors having a protective layer using selective etching
US6475906B1 (en) * 2001-07-05 2002-11-05 Promos Technologies, Inc. Gate contact etch sequence and plasma doping method for sub-150 NM DT-based DRAM devices
US6730553B2 (en) 2001-08-30 2004-05-04 Micron Technology, Inc. Methods for making semiconductor structures having high-speed areas and high-density areas
US6909152B2 (en) * 2002-11-14 2005-06-21 Infineon Technologies, Ag High density DRAM with reduced peripheral device area and method of manufacture
US6828238B1 (en) * 2003-06-03 2004-12-07 Micron Technology, Inc. Methods of forming openings extending through electrically insulative material to electrically conductive material
DE102004020938B3 (de) * 2004-04-28 2005-09-08 Infineon Technologies Ag Verfahren zum Herstellen einer ersten Kontaktlochebene in einem Speicherbaustein
TWI242797B (en) * 2004-06-01 2005-11-01 Nanya Technology Corp Method for forming self-aligned contact of semiconductor device
KR100753414B1 (ko) 2006-02-24 2007-08-30 주식회사 하이닉스반도체 반도체 소자의 제조방법
US8563425B2 (en) * 2009-06-01 2013-10-22 Advanced Micro Devices Selective local interconnect to gate in a self aligned local interconnect process

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5294822A (en) * 1989-07-10 1994-03-15 Texas Instruments Incorporated Polycide local interconnect method and structure
JP2643907B2 (ja) * 1995-05-12 1997-08-25 日本電気株式会社 半導体装置の製造方法
US5637525A (en) * 1995-10-20 1997-06-10 Micron Technology, Inc. Method of forming a CMOS circuitry
US5718800A (en) * 1995-11-08 1998-02-17 Micron Technology, Inc. Self-aligned N+/P+ doped polysilicon plugged contacts to N+/P+ doped polysilicon gates and to N+/P+ doped source/drain regions
KR100192521B1 (ko) * 1996-07-19 1999-06-15 구본준 반도체장치의 제조방법
TW368731B (en) * 1997-12-22 1999-09-01 United Microelectronics Corp Manufacturing method for self-aligned local-interconnect and contact

Also Published As

Publication number Publication date
TW402818B (en) 2000-08-21
JPH11135779A (ja) 1999-05-21
KR19990037416A (ko) 1999-05-25
US6300178B1 (en) 2001-10-09

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