JPWO2024070309A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2024070309A5 JPWO2024070309A5 JP2024549862A JP2024549862A JPWO2024070309A5 JP WO2024070309 A5 JPWO2024070309 A5 JP WO2024070309A5 JP 2024549862 A JP2024549862 A JP 2024549862A JP 2024549862 A JP2024549862 A JP 2024549862A JP WO2024070309 A5 JPWO2024070309 A5 JP WO2024070309A5
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- region
- notch
- pattern
- modified layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022158103 | 2022-09-30 | ||
| PCT/JP2023/029716 WO2024070309A1 (ja) | 2022-09-30 | 2023-08-17 | 基板処理方法及び基板処理システム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2024070309A1 JPWO2024070309A1 (https=) | 2024-04-04 |
| JPWO2024070309A5 true JPWO2024070309A5 (https=) | 2025-06-05 |
Family
ID=90477303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024549862A Pending JPWO2024070309A1 (https=) | 2022-09-30 | 2023-08-17 |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPWO2024070309A1 (https=) |
| KR (1) | KR20250078974A (https=) |
| CN (1) | CN119948602A (https=) |
| TW (1) | TW202430306A (https=) |
| WO (1) | WO2024070309A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102903522B1 (ko) * | 2020-04-02 | 2025-12-23 | 도쿄엘렉트론가부시키가이샤 | 기판 처리 방법 및 기판 처리 장치 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4232148B2 (ja) * | 2003-01-28 | 2009-03-04 | 株式会社Ｓｕｍｃｏ | 貼り合わせ基板の製造方法 |
| JP6286256B2 (ja) * | 2014-03-31 | 2018-02-28 | 株式会社東京精密 | ウエハマーキング・研削装置及びウエハマーキング・研削方法 |
| CN118263105A (zh) | 2018-03-14 | 2024-06-28 | 东京毅力科创株式会社 | 基板处理系统、基板处理方法以及计算机存储介质 |
| KR102903523B1 (ko) * | 2018-04-27 | 2025-12-23 | 도쿄엘렉트론가부시키가이샤 | 기판 처리 시스템 및 기판 처리 방법 |
| TWI832975B (zh) * | 2019-03-08 | 2024-02-21 | 日商東京威力科創股份有限公司 | 處理裝置及處理方法 |
| KR102810856B1 (ko) * | 2019-09-02 | 2025-05-20 | 삼성전자주식회사 | 반도체 소자 제조 장치, 반도체 소자 검사 장치 및 반도체 소자 제조 방법 |
| JP7386075B2 (ja) * | 2019-12-25 | 2023-11-24 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理システム |
-
2023
- 2023-08-17 KR KR1020257013709A patent/KR20250078974A/ko active Pending
- 2023-08-17 CN CN202380068148.6A patent/CN119948602A/zh active Pending
- 2023-08-17 WO PCT/JP2023/029716 patent/WO2024070309A1/ja not_active Ceased
- 2023-08-17 JP JP2024549862A patent/JPWO2024070309A1/ja active Pending
- 2023-09-14 TW TW112134990A patent/TW202430306A/zh unknown
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5074549B2 (ja) | 回路基板およびその製造方法 | |
| US20080012096A1 (en) | Semiconductor chip and method of forming the same | |
| JPWO2024070309A5 (https=) | ||
| TW201911397A (zh) | 處理襯底的方法 | |
| JPWO2021192854A5 (https=) | ||
| JPWO2021010286A5 (https=) | ||
| JPWO2023054010A5 (https=) | ||
| CN113078109B (zh) | 半导体结构的制作方法及半导体结构 | |
| JPWO2021010287A5 (https=) | ||
| JPWO2021010285A5 (https=) | ||
| JP2022139255A5 (https=) | ||
| JPWO2023157566A5 (https=) | ||
| CN116130355B (zh) | 干法刻蚀制作正梯形胶形的工艺 | |
| JP2024085189A5 (https=) | ||
| JP2010507260A (ja) | ウエハのバイア形成 | |
| US20060148129A1 (en) | Silicon direct bonding method | |
| JP4288573B2 (ja) | 半導体ウェハのチップ化方法 | |
| JP7663907B2 (ja) | 半導体装置の製造方法 | |
| JP3162970B2 (ja) | 半導体装置の製造方法 | |
| TW202430306A (zh) | 基板處理方法及基板處理系統 | |
| JP7658114B2 (ja) | 半導体チップの製造方法 | |
| JP2576257B2 (ja) | 半導体圧力センサの製造方法 | |
| JP2001127024A (ja) | 半導体装置及びその製造方法 | |
| JPWO2024241699A5 (https=) | ||
| JP2021100071A5 (https=) |