JPWO2021229740A5 - - Google Patents

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JPWO2021229740A5
JPWO2021229740A5 JP2022522426A JP2022522426A JPWO2021229740A5 JP WO2021229740 A5 JPWO2021229740 A5 JP WO2021229740A5 JP 2022522426 A JP2022522426 A JP 2022522426A JP 2022522426 A JP2022522426 A JP 2022522426A JP WO2021229740 A5 JPWO2021229740 A5 JP WO2021229740A5
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manufacturing
semiconductor device
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JP2022522426A
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JP7533575B2 (ja
JPWO2021229740A1 (https=
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JP2022522426A 2020-05-14 2020-05-14 半導体装置及びその製造方法 Active JP7533575B2 (ja)

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JP2024118650A JP7704265B2 (ja) 2020-05-14 2024-07-24 半導体装置及びその製造方法

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PCT/JP2020/019228 WO2021229740A1 (ja) 2020-05-14 2020-05-14 半導体装置及びその製造方法

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JPWO2021229740A1 JPWO2021229740A1 (https=) 2021-11-18
JPWO2021229740A5 true JPWO2021229740A5 (https=) 2023-06-05
JP7533575B2 JP7533575B2 (ja) 2024-08-14

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US (2) US12543353B2 (https=)
JP (2) JP7533575B2 (https=)
CN (1) CN115552604A (https=)
WO (1) WO2021229740A1 (https=)

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JP7302658B2 (ja) * 2019-06-18 2023-07-04 株式会社ソシオネクスト 半導体装置
JP7640861B2 (ja) * 2019-10-18 2025-03-06 株式会社ソシオネクスト 半導体集積回路装置
US20220359545A1 (en) * 2021-05-07 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory devices with dielectric fin structures
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US12527078B2 (en) 2021-12-21 2026-01-13 Intel Corporation Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation
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US20240105727A1 (en) * 2022-09-23 2024-03-28 Apple Inc. Vertical Transistor Cell Structures Utilizing Topside and Backside Resources
US20250006730A1 (en) * 2023-06-27 2025-01-02 International Business Machines Corporation Stacked transistors with dielectric insulator layers
US20250048677A1 (en) * 2023-08-02 2025-02-06 International Business Machines Corporation Backside power rail to backside contact connection
EP4539635A1 (en) * 2023-10-13 2025-04-16 Samsung Electronics Co., Ltd Semiconductor device, array structure including the semiconductor device, and method of manufacturing the semiconductor device
US20250185356A1 (en) * 2023-12-05 2025-06-05 International Business Machines Corporation Self-aligned backside gate cut dielectric with air gap
US20250254988A1 (en) * 2024-02-05 2025-08-07 Samsung Electronics Co., Ltd. Semiconductor device including stacked forksheet transistor structure with isolation wall
WO2025211200A1 (ja) * 2024-04-01 2025-10-09 株式会社ソシオネクスト 半導体集積回路装置

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JP2001358319A (ja) * 2000-06-12 2001-12-26 Mitsubishi Electric Corp 交差ゲート構造を持つ半導体装置およびその製造方法
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
WO2013095341A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
EP3127862B1 (en) 2015-08-06 2018-04-18 IMEC vzw A method of manufacturing a gate-all-around nanowire device comprising two different nanowires
US9570395B1 (en) 2015-11-17 2017-02-14 Samsung Electronics Co., Ltd. Semiconductor device having buried power rail
TWI739879B (zh) * 2016-08-10 2021-09-21 日商東京威力科創股份有限公司 用於半導體裝置的延伸區域
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