WO2021229740A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2021229740A1
WO2021229740A1 PCT/JP2020/019228 JP2020019228W WO2021229740A1 WO 2021229740 A1 WO2021229740 A1 WO 2021229740A1 JP 2020019228 W JP2020019228 W JP 2020019228W WO 2021229740 A1 WO2021229740 A1 WO 2021229740A1
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Prior art keywords
semiconductor
semiconductor layer
semiconductor region
region
layer
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English (en)
French (fr)
Japanese (ja)
Inventor
晴彦 芹澤
達夫 千々松
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Socionext Inc
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Socionext Inc
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Priority to CN202080100676.1A priority Critical patent/CN115552604A/zh
Priority to PCT/JP2020/019228 priority patent/WO2021229740A1/ja
Priority to JP2022522426A priority patent/JP7533575B2/ja
Publication of WO2021229740A1 publication Critical patent/WO2021229740A1/ja
Priority to US17/982,005 priority patent/US12543353B2/en
Anticipated expiration legal-status Critical
Priority to JP2024118650A priority patent/JP7704265B2/ja
Priority to US19/407,255 priority patent/US20260090041A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same.
  • CFET complementary field effect transistor
  • Forksheet transistor An element called a forksheet transistor is also known.
  • nanowire or nanosheet channels are arranged so as to sandwich a wall-shaped insulating film in between.
  • Fork sheet transistors are also suitable for miniaturization of semiconductor devices.
  • An object of the present invention is to provide a semiconductor device capable of further miniaturization and a method for manufacturing the same.
  • the semiconductor device sandwiches the substrate, the first semiconductor layer arranged on the substrate, and the first semiconductor layer on the substrate in the first direction in a plan view.
  • the first semiconductor region and the second semiconductor region arranged in the above, the second semiconductor layer arranged above the first semiconductor layer, and the first semiconductor region and the second semiconductor region, respectively.
  • a third semiconductor region and a fourth semiconductor region arranged with the second semiconductor layer interposed therebetween, and on the substrate, the first direction in a plan view.
  • a third semiconductor layer arranged side by side with the first semiconductor layer in a second direction different from the above, and the third semiconductor layer on the substrate in the first direction in a plan view.
  • a resistance element including a structure such as a CFET.
  • FIG. 1 is a diagram showing a configuration of a circuit included in the semiconductor device according to the embodiment.
  • FIG. 2 is a schematic diagram (No. 1) showing the planar configuration of the buffer.
  • FIG. 3 is a schematic diagram (No. 2) showing the planar configuration of the buffer.
  • FIG. 4 is a cross-sectional view (No. 1) showing the buffer.
  • FIG. 5 is a cross-sectional view (No. 2) showing the buffer.
  • FIG. 6 is a cross-sectional view (No. 3) showing the buffer.
  • FIG. 7 is a cross-sectional view (No. 4) showing the buffer.
  • FIG. 8 is a cross-sectional view (No. 5) showing the buffer.
  • FIG. 9 is a plan view (No. 1) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 10 is a plan view (No. 2) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 11 is a plan view (No. 3) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 12 is a plan view (No. 4) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 13 is a plan view (No. 5) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 14 is a plan view (No. 6) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 15 is a plan view (No. 7) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 16 is a plan view (No. 7) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 17 is a plan view (No. 9) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 18 is a plan view (No. 10) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 19 is a plan view (No. 11) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 20 is a plan view (No. 12) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 21 is a plan view (No. 13) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 22 is a plan view (No. 14) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 23 is a plan view (No. 15) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 24 is a plan view (No. 16) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 25 is a cross-sectional view (No. 1) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 26 is a cross-sectional view (No. 2) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 27 is a cross-sectional view (No. 3) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 28 is a cross-sectional view (No. 4) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 29 is a cross-sectional view (No. 15) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 24 is a plan view (No. 16) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 30 is a cross-sectional view (No. 6) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 31 is a cross-sectional view (No. 7) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 32 is a cross-sectional view (No. 8) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 33 is a cross-sectional view (No. 9) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 34 is a cross-sectional view (No. 10) showing a method of manufacturing the semiconductor device according to the embodiment.
  • FIG. 35 is a cross-sectional view (No.
  • FIG. 11 showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 36 is a cross-sectional view (No. 12) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 37 is a cross-sectional view (No. 13) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 38 is a cross-sectional view (No. 14) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 39 is a cross-sectional view (No. 15) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 40 is a cross-sectional view (No. 16) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 41 is a cross-sectional view (No.
  • FIG. 42 is a cross-sectional view (No. 18) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 43 is a cross-sectional view (No. 19) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 44 is a cross-sectional view (No. 20) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 45 is a cross-sectional view (No. 21) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 46 is a cross-sectional view (No. 22) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 47 is a cross-sectional view (No.
  • FIG. 48 is a cross-sectional view (No. 24) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 49 is a cross-sectional view (No. 25) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 50 is a cross-sectional view (No. 26) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 51 is a cross-sectional view (No. 27) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 52 is a cross-sectional view (No. 28) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 53 is a cross-sectional view (No.
  • FIG. 54 is a cross-sectional view (No. 30) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 55 is a cross-sectional view (No. 31) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 56 is a cross-sectional view (No. 32) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 57 is a cross-sectional view (No. 33) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 58 is a cross-sectional view (No. 34) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 59 is a cross-sectional view (No. 30) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 60 is a cross-sectional view (No. 36) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 61 is a cross-sectional view (No. 37) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 62 is a cross-sectional view (No. 38) showing a method of manufacturing a semiconductor device according to an embodiment.
  • FIG. 63 is a cross-sectional view (No. 39) showing a method of manufacturing a semiconductor device according to an embodiment.
  • the embodiment will be specifically described with reference to the attached drawings.
  • components having substantially the same functional configuration may be designated by the same reference numerals to omit duplicate explanations.
  • the two directions parallel to the surface of the substrate and orthogonal to each other are defined as the X direction and the Y direction, and the direction perpendicular to the surface of the substrate is defined as the Z direction.
  • the n-channel field-effect transistor may be referred to as an nFET
  • the p-channel field-effect transistor may be referred to as a pFET.
  • the agreement of arrangement in the present disclosure does not strictly exclude those that are inconsistent due to manufacturing variation, and even if the arrangement is misaligned due to manufacturing variation. It can be considered that the arrangements match.
  • FIG. 1 is a diagram showing a configuration of a circuit included in the semiconductor device according to the embodiment.
  • the semiconductor device 100 has a buffer BU, a VDD wiring to which the power potential of VDD is supplied, and a VSS wiring to which the power potential of VSS is supplied.
  • VDD wiring is sometimes called power supply wiring.
  • the power supply potential of VSS is, for example, the ground potential, and the VSS wiring may be called the ground wiring.
  • the buffer BU has an inverter 1 and an inverter 2.
  • the input signal IN is input to the inverter 1, the output of the inverter 1 is input to the inverter 2, and the output signal OUT is output from the inverter 2.
  • the inverter 1 has a p-channel field effect transistor (pFET) 1P and an n-channel field effect transistor (nFET) 1N
  • the inverter 2 has a pFET 2P and an nFET 2N.
  • FIGS. 2 and 3 are schematic views showing a planar configuration of the buffer BU.
  • FIG. 2 mainly shows the layout of nFET1N and pFET2P.
  • FIG. 3 mainly shows the layout of pFET1P and nFET2N. Except for the structures shown in both FIGS. 2 and 3, the structures shown in FIG. 3 are located above the structures shown in FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 8 are cross-sectional views showing a buffer BU.
  • FIG. 4 corresponds to a cross-sectional view taken along the line IV-IV in FIGS. 2 and 3.
  • FIG. 5 corresponds to a cross-sectional view taken along the VV line in FIGS. 2 and 3.
  • FIG. 6 corresponds to a cross-sectional view taken along the line VI-VI in FIGS. 2 and 3.
  • FIG. 7 corresponds to a cross-sectional view taken along the line VII-VII in FIGS. 2 and 3.
  • FIG. 8 corresponds to a cross-sectional view taken along the line VIII-VIII in FIGS. 2 and 3.
  • the element separation film 102 is formed on the surface of the substrate 101.
  • the element separation membrane 102 is formed by, for example, an STI (Shallow Trench Isolation) method.
  • a plurality of grooves extending in the X direction are formed in the substrate 101 and the element separation membrane 102, and power supply lines 910 and 920 are formed in these grooves via the insulating film 104.
  • the surfaces of the power supply lines 910 and 920 are covered with the insulating film 103.
  • the surface of the element separation membrane 102 and the surface of the insulating film 103 may or may not be flush with the surface of the substrate 101.
  • the power lines 910 and 920 are embedded in the substrate 101.
  • the power supply lines 910 and 920 having such a structure may be referred to as BPR (Buried Power Rail).
  • the power supply line 910 corresponds to the VDD wiring
  • the power supply line 920 corresponds to the VSS wiring.
  • two regions 10 and 20 arranged in the X direction are defined by the element separation membrane 102.
  • the inverter 1 is formed in the region 10
  • the inverter 2 is formed in the region 20.
  • the laminated transistor structure 11 is formed on the substrate 101.
  • the laminated transistor structure 11 includes a gate electrode 110, nanosheets 121 and 122, a gate insulating film 130, and a spacer 140.
  • the gate electrode 110 extends in the Y direction and rises in the Z direction.
  • the nanosheets 121 and 122 penetrate the gate electrode 110 in the X direction and are arranged in the Y and Z directions.
  • the gate insulating film 130 is formed between the gate electrode 110 and the nanosheets 121 and 122.
  • the gate electrode 110 and the gate insulating film 130 are formed so as to recede from both ends of the nanosheets 121 and 122, and a spacer 140 is formed in the recessed portions.
  • a spacer 140 is formed between the n-type semiconductor layer 161 and the p-type semiconductor layer 163, which will be described later, and the gate electrode 110 in the X direction.
  • the number of nanosheets 121 and 122 arranged in the Z direction is 2, respectively, and the two nanosheets 122 are arranged above the two nanosheets 121.
  • the thickness of the nanosheets 121 and 122 is, for example, about 5 nm.
  • the number of nanosheets 121 and 122 may be 1 or 3 or more, respectively. Further, the numbers of the nanosheets 121 and the nanosheets 122 may be the same or different.
  • two n-type semiconductor layers 161 in contact with the end of the nanosheet 121 are formed so as to sandwich the gate electrode 110 in the X direction.
  • Two local wirings 162 in contact with the n-type semiconductor layer 161 are formed so as to sandwich the gate electrode 110 in the X direction.
  • Two p-type semiconductor layers 163 in contact with the end of the nanosheet 122 are formed so as to sandwich the gate electrode 110 in the X direction.
  • Two local wirings 164 in contact with the p-type semiconductor layer 163 are formed so as to sandwich the gate electrode 110 in the X direction.
  • An insulating film 31 is formed between the local wiring 162 and the local wiring 164.
  • the n-type semiconductor layer 161 is an n-type Si layer
  • the p-type semiconductor layer 163 is a p-type SiGe layer.
  • silicon oxide, silicon nitride, or the like can be used for the insulating film 31.
  • a contact hole 312 is formed in the insulating film 31 between the local wiring 162 and the local wiring 164.
  • the local wiring 164 is electrically connected to the local wiring 162 through a conductor in the contact hole 312.
  • a part of the gate electrode 110, a nanosheet 121, a part of the gate insulating film 130, and an n-type semiconductor layer 161 are included in the nFET1N.
  • one n-type semiconductor layer 161 functions as a source region
  • the other n-type semiconductor layer 161 functions as a drain region
  • the nanosheet 121 functions as a channel.
  • a part of the gate electrode 110, a nanosheet 122, a part of the gate insulating film 130, and a p-type semiconductor layer 163 are included in the pFET 1P.
  • one p-type semiconductor layer 163 functions as a source region, the other p-type semiconductor layer 163 functions as a drain region, and the nanosheet 122 functions as a channel.
  • the n-type semiconductor layer 161 and the substrate 101 may be electrically connected or may be electrically separated by an insulating film formed between them.
  • the laminated transistor structure 21 is formed on the substrate 101.
  • the laminated transistor structure 21 includes a gate electrode 210, nanosheets 221 and 222, a gate insulating film 230, and a spacer 240.
  • the gate electrode 210 extends in the Y direction and rises in the Z direction.
  • the nanosheets 221 and 222 penetrate the gate electrode 210 in the X direction and are arranged in the Y direction and the Z direction.
  • the gate insulating film 230 is formed between the gate electrode 210 and the nanosheets 221 and 222.
  • the gate electrode 210 and the gate insulating film 230 are formed so as to recede from both ends of the nanosheets 221 and 222, and a spacer 240 is formed in the retracted portion.
  • a spacer 240 is formed between the p-type semiconductor layer 261 and the n-type semiconductor layer 263, which will be described later, and the gate electrode 210 in the X direction.
  • the number of nanosheets 221 and 222 arranged in the Z direction is 2, respectively, and the two nanosheets 222 are arranged above the two nanosheets 221.
  • the thickness of the nanosheets 221 and 222 is, for example, 10 nm or less, preferably 5 nm or less.
  • the number of nanosheets 221 and 222 may be 1 or 3 or more, respectively. Further, the numbers of the nanosheets 221 and the nanosheets 222 may be the same or different.
  • two p-type semiconductor layers 261 in contact with the end portion of the nanosheet 221 are formed so as to sandwich the gate electrode 210 in the X direction.
  • Two local wirings 262 in contact with the p-type semiconductor layer 261 are formed so as to sandwich the gate electrode 210 in the X direction.
  • Two n-type semiconductor layers 263 in contact with the end of the nanosheet 222 are formed so as to sandwich the gate electrode 210 in the X direction.
  • Two local wirings 264 in contact with the n-type semiconductor layer 263 are formed so as to sandwich the gate electrode 210 in the X direction.
  • An insulating film 32 is formed between the local wiring 262 and the local wiring 264.
  • the p-type semiconductor layer 261 is a p-type SiGe layer
  • the n-type semiconductor layer 263 is an n-type Si layer.
  • silicon oxide, silicon nitride, or the like can be used for the insulating film 32.
  • a contact hole 322 is formed in the insulating film 32 between the local wiring 262 and the local wiring 264.
  • the local wiring 264 is electrically connected to the local wiring 262 through a conductor in the contact hole 322.
  • the p-type semiconductor layer 261 and the substrate 101 may be electrically connected or may be electrically separated by an insulating film formed between them.
  • a part of the gate electrode 210, a nanosheet 221 and a part of the gate insulating film 230 and a p-type semiconductor layer 261 are included in the pFET 2P.
  • one p-type semiconductor layer 261 functions as a source region
  • the other p-type semiconductor layer 261 functions as a drain region
  • the nanosheet 221 functions as a channel.
  • a part of the gate electrode 210, a nanosheet 222, a part of the gate insulating film 230, and an n-type semiconductor layer 263 are included in the nFET 2N.
  • one n-type semiconductor layer 263 functions as a source region
  • the other n-type semiconductor layer 263 functions as a drain region
  • the nanosheet 222 functions as a channel.
  • an insulating film is formed between the gate electrodes 110 and 210 and the substrate 101, and they are electrically separated from each other.
  • the local wiring 162 extends in the Y direction.
  • the local wiring 162 extends above the power supply line 910.
  • a contact hole 311 is formed in the insulating film 103 between the local wiring 162 and the power supply line 910.
  • the local wiring 162 is connected to the power supply line 910 through a conductor in the contact hole 311.
  • the local wiring 262 extends in the Y direction.
  • the local wiring 262 extends above the power line 920.
  • a contact hole 321 is formed in the insulating film 103 between the local wiring 262 and the power supply line 920.
  • the local wiring 262 is connected to the power supply line 920 through a conductor in the contact hole 321.
  • An insulating wall 50 is provided between the area 10 and the area 20 on the substrate 101.
  • the wall 50 extends in the X direction and rises in the Z direction.
  • the wall 50 comprises a side surface 51 and a side surface 52 opposite to the side surface 51, the side surface 51 in contact with the nanosheets 121 and 122, and the side surface 52 in contact with the nanosheets 221 and 222.
  • the width of the wall 50 that is, the distance between the side surface 51 and the side surface 52 is, for example, 15 nm or less, preferably 8 nm or less.
  • the sidewall 55 is formed so as to sandwich the gate electrodes 110 and 210 together with the wall 50 in the Y direction.
  • An insulating film 61 is formed on the side of the sidewall 55.
  • the insulating film 63 is formed between the insulating film 61 and the local wiring 164 and 264, and as shown in FIG. 6, the insulating film 62 is formed between the insulating film 61 and the local wiring 262. Has been done.
  • An insulating film 64 is formed on the wall 50, the gate electrodes 110 and 210, the spacers 140 and 240, the local wirings 164 and 264, the sidewall 55, and the insulating films 61 and 63, and the insulating film 64 is formed on the insulating film 64.
  • the insulating film 65 is formed on the surface.
  • Contact holes 313 reaching the local wiring 162 are formed in the insulating films 64, 63 and 31, and contact holes 323 reaching the local wiring 262 are formed in the insulating films 64, 63 and 32.
  • the contact hole 313 is formed above the contact hole 311 and the contact hole 323 is formed above the contact hole 321.
  • Signal lines 411 and 421 are formed in the insulating film 64.
  • the signal line 411 is connected to the local wiring 162 through a conductor in the contact hole 313.
  • the signal line 421 is connected to the local wiring 262 through a conductor in the contact hole 323.
  • the insulating film 64 is formed with a contact hole 314 reaching the gate electrode 110, a contact hole 315 reaching one local wiring 164, and a contact hole 316 reaching the other local wiring 164.
  • the insulating film 64 is formed with a contact hole 324 reaching the gate electrode 210, a contact hole 325 reaching one local wiring 264, and a contact hole 326 reaching the other local wiring 264.
  • Signal lines 412, 413, 414, 422, 423 and 424 are formed in the insulating film 64.
  • the signal line 412 is connected to the gate electrode 110 through a conductor in the contact hole 314.
  • the signal line 413 is connected to one local wiring 164 through a conductor in the contact hole 315.
  • the signal line 414 is connected to the other local wiring 164 through a conductor in the contact hole 316.
  • the signal line 423 is connected to the gate electrode 210 through a conductor in the contact hole 324.
  • the signal line 424 is connected to one local wiring 264 through a conductor in the contact hole 325.
  • the signal line 422 is connected to the other local wiring 264 through a conductor in the contact hole 326.
  • the insulating film 65 is formed with a contact hole 317 reaching the signal line 414, a contact hole 318 reaching the signal line 413, and a contact hole 319 reaching the signal line 411.
  • the insulating film 65 is formed with a contact hole 327 reaching the signal line 423, a contact hole 328 reaching the signal line 421, and a contact hole 329 reaching the signal line 424.
  • Signal lines 431, 432 and 433 are formed in the insulating film 65.
  • the signal line 431 is connected to the signal line 413 through the conductor in the contact hole 318, and is connected to the signal line 421 through the conductor in the contact hole 328.
  • the signal line 432 is connected to the signal line 414 through the conductor in the contact hole 317, and is connected to the signal line 423 through the conductor in the contact hole 327.
  • the signal line 433 is connected to the signal line 411 through the conductor in the contact hole 319, and is connected to the signal line 424 through the conductor in the contact hole 329.
  • the input signal IN is input to the signal line 412, and the output signal OUT is output from the signal line 422.
  • ruthenium (Ru), molybdenum (Mo), cobalt (Co), tungsten (W), or the like is used as the material for the power supply lines 910 and 920.
  • copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co) and the like are used as materials for the signal lines 411 to 414, 421 to 424 and 431 to 433.
  • a conductive base film for example, a tantalum (Ta) film or tantalum nitride (TaN) film, but when ruthenium is used, the base film is used. It does not have to be formed.
  • copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), tungsten (W), or the like is used as the material for the local wiring 162, 164, 262, and 264.
  • a conductive base film for example, a titanium (Ti) film or titanium nitride (TiN) film, but when molybdenum or ruthenium is used, it is below. It is not necessary to form the ground film.
  • the conductor (via) in the contact hole for example, the same material as the material for local wiring can be used.
  • a semiconductor such as silicon (Si) can be used for the substrate 101.
  • semiconductors such as silicon (Si) can be used for the nanosheets 121, 122, 221 and 222.
  • semiconductors such as silicon (Si) can be used for the nanosheets 121, 122, 221 and 222.
  • semiconductors such as silicon (Si) can be used for the p-type semiconductor layers 163 and 261
  • semiconductors such as silicon, silicon carbide (SiC), and silicon germanium (SiGe) containing boron (B) as p-type impurities can be used.
  • semiconductors such as silicon, silicon carbide, and silicon germanium containing phosphorus (P) as n-type impurities can be used.
  • conductive materials such as titanium (Ti), titanium nitride (TiN), and polycrystalline silicon (polySi) can be used for the gate electrodes 110 and 210.
  • high dielectric materials such as hafnium oxide, aluminum oxide, hafnium and aluminum oxide can be used for the gate insulating films 130 and 230.
  • the gate insulating film 130 formed on the nanosheet 121 and the gate insulating film 130 formed on the nanosheet 122 may contain different materials.
  • the gate insulating film 230 formed on the nanosheet 221 and the gate insulating film 230 formed on the nanosheet 222 may contain different materials.
  • the local wiring and signal lines are formed by the dual damascene method together with the contact holes arranged below them. Further, the local wiring and the signal line may be formed by the single damascene method separately from the contact holes arranged below them.
  • silicon oxide, silicon nitride or the like can be used as the material of the sidewall 55, the spacers 140 and 240, and the insulating wall 50.
  • FIGS. 9 to 24 are plan views showing a method of manufacturing a semiconductor device according to an embodiment.
  • 25 to 37 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment.
  • 25 to 37 show changes in cross section along lines IV-IV in FIGS. 2 and 3.
  • 38 to 44 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment.
  • 38 to 44 show changes in cross section along the VV line in FIGS. 2 and 3.
  • 45 to 48 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment.
  • 45 to 48 show changes in cross section along lines VI-VI in FIGS. 2 and 3.
  • 49 to 63 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment. 49 to 63 show changes in cross section along lines VII-VII in FIGS. 2 and 3. In FIGS. 12 to 24, the insulating film other than the gate insulating film is omitted.
  • the SiGe film 71, the Si film 81, the SiGe film 72, the Si film 82, the SiGe film 73, the Si film 83, the SiGe film 74, and the Si film are placed on the substrate 101.
  • the 84 and the SiGe film 75 are formed.
  • the Si films 81 and 82 become nanosheets 121 and 221 and the Si films 83 and 84 become nanosheets 122 and 222.
  • the thickness of the Si films 81 to 84 is, for example, about 5 nm.
  • the thickness of the SiGe film 71 to 75 is, for example, about 5 nm to 8 nm.
  • the SiGe film 73 may be thicker than the SiGe films 71, 72, 74 and 75.
  • the SiGe films 71 to 75 and the Si films 81 to 84 are formed by, for example, an epitaxial growth method.
  • the laminated layers of the SiGe films 71 to 75 and the Si films 81 to 84 are subsequently etched and patterned into a plate shape protruding from the substrate 101.
  • fins 91 and 92 extending in the Y direction are formed so as to correspond to the regions 10 and 20, respectively.
  • the fins 91 and 92 are arranged in the X direction.
  • a groove 105 for the element separation film 102 is formed on the surface of the substrate 101 on the side of the fins 91 and 92 in a plan view.
  • the element separation membrane 102 is formed in the groove 105.
  • the element separation membrane 102 defines, for example, two regions 10 and 20 arranged in the X direction.
  • an insulating film 106 that covers the upper surfaces and side surfaces of the fins 91 and 92 and covers the upper surface of the element separation film 102 is formed.
  • the insulating film 106 is formed so as to fill the gap between the fins 91 and 92.
  • the insulating wall 50 is formed by etching the insulating film 106 so as to remain in the gap between the fins 91 and 92.
  • the wall 50 has a side surface 51 in contact with the fin 91 and a side surface 52 in contact with the fin 92.
  • the insulating film 106 may be formed before the element separation film 102 is formed, the insulating film 106 may be etched so as to remain in the gap between the fins 91 and 92, and then the element separation film 102 may be formed. ..
  • a wall 50 is formed in the groove 105 between the fins 91 and 92 instead of the element separation membrane 102.
  • the element separation film 102 and the insulating film 106 may be formed collectively, and then the insulating film 106 may be etched so as to remain in the gap between the fins 91 and 92.
  • a plurality of grooves extending in the X direction for the power supply lines 910 and 920 are formed in the element separation membrane 102 and the substrate 101, and are insulated along the bottom surface and the side surface of these grooves.
  • the film 104 is formed.
  • the power supply lines 910 and 920 are formed on the insulating film 104, and the insulating film 103 is formed on the power supply lines 910 and 920.
  • the formation of the groove, the formation of the insulating film 104, the formation of the power supply lines 910 and 920, and the formation of the insulating film 103 may be performed before the formation of the wall 50.
  • the sacrifice gate 107 and the sidewall 55 are formed.
  • the sacrificial gate 107 is, for example, a polycrystalline silicon film.
  • the sidewall 55 can be formed, for example, by forming an insulating film and etching back.
  • the insulating film 61 is formed.
  • a silicon oxide film is formed, and the upper surface of the silicon oxide film is polished by chemical mechanical polishing (CMP) until the sacrificial gate 107 and the sidewall 55 are exposed.
  • CMP chemical mechanical polishing
  • the insulating film 61 is selectively removed and exposed from the sacrificial gate 107 and the sidewall 55 of the fins 91 and 92 in the region where the gate electrode and the local wiring are to be formed. Remove the removed part.
  • both ends of the SiGe films 71 to 75 are retracted in the X direction by isotropic etching.
  • the portion of the Si film 81 and 82 in the fin 91 becomes the nanosheet 121
  • the portion of the Si film 81 and 82 in the fin 92 becomes the nanosheet 221
  • the portion of the Si film 83 and 84 in the fin 91 becomes the nanosheet 122
  • the Si film The portion of the fins 92 of 83 and 84 becomes the nanosheet 222.
  • a spacer 140 is formed in the portion where the SiGe films 71 to 75 are retracted.
  • the cover film 108 is formed so as to cover both end faces of the nanosheets 122 and 222 in the X direction.
  • the n-type semiconductor layer 161 is epitaxially grown on the side surface of the nanosheet 121, and the p-type semiconductor layer 261 is epitaxially grown on the side surface of the nanosheet 221.
  • phosphine (PH 3 ) is used in the n-type semiconductor layer 161 to introduce phosphorus (P) as an n-type impurity
  • diborane (B 2 H 6 ) is used in the p-type semiconductor layer 261.
  • Boron (B) is introduced as a p-type impurity. Either of the n-type semiconductor layer 161 and the p-type semiconductor layer 261 may be formed first.
  • the cover film 108 is also formed on the side surface of the nanosheet 121 or 221 on which the semiconductor layer to be formed later is grown among the n-type semiconductor layer 161 and the p-type semiconductor layer 261, and after the semiconductor layer formed earlier is grown. It is preferable to remove the semiconductor layer to be formed later from the growing portion.
  • the insulating film 62 is formed, and two local wirings 162 in contact with the n-type semiconductor layer 161 and two local wirings in contact with the p-type semiconductor layer 261 are formed.
  • Form 262 and. Local wiring 162 and 262 can be formed at the same time.
  • the local wirings 162 and 262 can be formed, for example, by forming a conductive film and etching back.
  • the insulating film 31 is formed on the local wiring 162, and the insulating film 32 is formed on the local wiring 262.
  • the insulating films 31 and 32 can be formed at the same time.
  • the contact holes 311 and 321 are formed in the insulating film 103, one of the local wirings 162 is formed so as to be in contact with the power supply line 910, and the other local wiring 262 is formed of the power supply line 920. It may be formed so as to be in contact with.
  • the cover film 108 is removed, the p-type semiconductor layer 163 is epitaxially grown on the side surface of the nanosheet 122, and the n-type semiconductor layer is formed on the side surface of the nanosheet 222. 263 is epitaxially grown.
  • diborane (B 2 H 6 ) is used in the p-type semiconductor layer 163 to introduce boron (B) as a p-type impurity
  • phosphin (PH 3 ) is used in the n-type semiconductor layer 263.
  • Phosphorus (P) is introduced as an n-type impurity.
  • Either of the p-type semiconductor layer 163 and the n-type semiconductor layer 263 may be formed first.
  • the cover film 108 grows the semiconductor layer to be formed earlier while leaving it on the side surface of the nanosheet 122 or 222 for growing the semiconductor layer to be formed later among the p-type semiconductor layer 163 and the n-type semiconductor layer 263, and then grows the semiconductor layer. , It is preferable to remove the whole.
  • the insulating film 63 is formed, and the local wiring 164 in contact with the p-type semiconductor layer 163 and the local wiring 264 in contact with the n-type semiconductor layer 263 are formed.
  • Local wiring 164 and 264 can be formed at the same time.
  • the local wirings 164 and 264 can be formed, for example, by forming a conductive film and etching back.
  • contact holes 312 and 322 are formed in the insulating films 31 and 32, respectively, one local wiring 164 is formed so as to be in contact with the local wiring 162, and one local wiring 264 is formed. It may be formed so as to be in contact with the local wiring 262.
  • the SiGe films 71 to 75 are removed. As a result, spaces are formed around the nanosheets 121, 122, 221 and 222.
  • the gate insulating films 130 and 230 are formed around the nanosheets 121, 122, 221 and 222.
  • the gate insulating films 130 and 230 can be formed by a deposition method such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.
  • the gate insulating films 130 and 230 are also formed on the surface of the substrate 101 and the like, but are not shown.
  • the gate electrodes 110 and 210 are formed, and for example, the insulating film 61 and the like are polished until the upper surface of the wall 50 is exposed, and the gate electrodes are formed. Flatten the top surfaces of 110 and 210. In this way, the laminated transistor structure 11 is formed in the region 10, and the laminated transistor structure 21 is formed in the region 20.
  • an insulating film 64 is formed, contact holes 313 to 316 and 323 to 326 are formed, and signal lines 411 to 414 and 421 to 424 are formed. To form. Subsequently, the insulating film 65 is formed, contact holes 317 to 319 and 327 to 329 are formed, and signal lines 431 to 433 are formed.
  • the semiconductor device 100 is completed by appropriately forming upper layer wiring and the like.
  • the circuit included in the semiconductor device of the present disclosure is not limited to a buffer in which two inverters are connected in series.
  • the connection relationship between the local wiring and the signal line is different from the above embodiment.
  • a circuit in which two inverters are connected in parallel may be included in the semiconductor device of the present disclosure, and two inverters independent of each other may be included. May be included in the semiconductor device of the present disclosure.
  • first to fourth semiconductor regions may be of the same conductive type to each other, and the fifth to eighth semiconductor regions may be of the same conductive type to each other.
  • all the conductive types of the semiconductor region connected to the semiconductor layer (nanosheet) in contact with the side surface 51 are N-type, and all the conductive types of the semiconductor region connected to the semiconductor layer (nanosheet) in contact with the side surface 52 are P-type. May be.
  • the first to eighth semiconductor regions may be of the same conductive type.
  • the power supply lines 910 and 920 may not be embedded in the substrate 101, and may be provided above the insulating film 61, for example.
  • the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. With respect to these points, the gist of the present invention can be changed to the extent that the gist of the present invention is not impaired, and can be appropriately determined according to the application form thereof.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
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US17/982,005 US12543353B2 (en) 2020-05-14 2022-11-07 Semiconductor device and semiconductor device manufacturing method
JP2024118650A JP7704265B2 (ja) 2020-05-14 2024-07-24 半導体装置及びその製造方法
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