JPWO2021229740A1 - - Google Patents

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Publication number
JPWO2021229740A1
JPWO2021229740A1 JP2022522426A JP2022522426A JPWO2021229740A1 JP WO2021229740 A1 JPWO2021229740 A1 JP WO2021229740A1 JP 2022522426 A JP2022522426 A JP 2022522426A JP 2022522426 A JP2022522426 A JP 2022522426A JP WO2021229740 A1 JPWO2021229740 A1 JP WO2021229740A1
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JP
Japan
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Application number
JP2022522426A
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Japanese (ja)
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JP7533575B2 (ja
JPWO2021229740A5 (https=
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Publication of JPWO2021229740A5 publication Critical patent/JPWO2021229740A5/ja
Priority to JP2024118650A priority Critical patent/JP7704265B2/ja
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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • H10D62/118Nanostructure semiconductor bodies
    • H10D62/119Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/014Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6757Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/017Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188Manufacturing their isolation regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H10D88/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
JP2022522426A 2020-05-14 2020-05-14 半導体装置及びその製造方法 Active JP7533575B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024118650A JP7704265B2 (ja) 2020-05-14 2024-07-24 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/019228 WO2021229740A1 (ja) 2020-05-14 2020-05-14 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2024118650A Division JP7704265B2 (ja) 2020-05-14 2024-07-24 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JPWO2021229740A1 true JPWO2021229740A1 (https=) 2021-11-18
JPWO2021229740A5 JPWO2021229740A5 (https=) 2023-06-05
JP7533575B2 JP7533575B2 (ja) 2024-08-14

Family

ID=78525494

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2022522426A Active JP7533575B2 (ja) 2020-05-14 2020-05-14 半導体装置及びその製造方法
JP2024118650A Active JP7704265B2 (ja) 2020-05-14 2024-07-24 半導体装置及びその製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2024118650A Active JP7704265B2 (ja) 2020-05-14 2024-07-24 半導体装置及びその製造方法

Country Status (4)

Country Link
US (2) US12543353B2 (https=)
JP (2) JP7533575B2 (https=)
CN (1) CN115552604A (https=)
WO (1) WO2021229740A1 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7302658B2 (ja) * 2019-06-18 2023-07-04 株式会社ソシオネクスト 半導体装置
JP7640861B2 (ja) * 2019-10-18 2025-03-06 株式会社ソシオネクスト 半導体集積回路装置
US20220359545A1 (en) * 2021-05-07 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory devices with dielectric fin structures
EP4199052B1 (en) * 2021-12-17 2024-08-21 IMEC vzw Metallization scheme for an integrated circuit
US12527078B2 (en) 2021-12-21 2026-01-13 Intel Corporation Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation
US12310064B2 (en) * 2022-07-29 2025-05-20 International Business Machines Corporation Isolation pillar structures for stacked device structures
US20240105727A1 (en) * 2022-09-23 2024-03-28 Apple Inc. Vertical Transistor Cell Structures Utilizing Topside and Backside Resources
US20250006730A1 (en) * 2023-06-27 2025-01-02 International Business Machines Corporation Stacked transistors with dielectric insulator layers
US20250048677A1 (en) * 2023-08-02 2025-02-06 International Business Machines Corporation Backside power rail to backside contact connection
EP4539635A1 (en) * 2023-10-13 2025-04-16 Samsung Electronics Co., Ltd Semiconductor device, array structure including the semiconductor device, and method of manufacturing the semiconductor device
US20250185356A1 (en) * 2023-12-05 2025-06-05 International Business Machines Corporation Self-aligned backside gate cut dielectric with air gap
US20250254988A1 (en) * 2024-02-05 2025-08-07 Samsung Electronics Co., Ltd. Semiconductor device including stacked forksheet transistor structure with isolation wall
WO2025211200A1 (ja) * 2024-04-01 2025-10-09 株式会社ソシオネクスト 半導体集積回路装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10424639B1 (en) * 2018-04-19 2019-09-24 International Business Machines Corporation Nanosheet transistor with high-mobility channel
US20190305104A1 (en) * 2018-04-02 2019-10-03 International Business Machines Corporation Nanosheet transistor with dual inner airgap spacers
US10510620B1 (en) * 2018-07-27 2019-12-17 GlobalFoundries, Inc. Work function metal patterning for N-P space between active nanostructures
US10559566B1 (en) * 2018-09-17 2020-02-11 International Business Machines Corporation Reduction of multi-threshold voltage patterning damage in nanosheet device structure

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358319A (ja) * 2000-06-12 2001-12-26 Mitsubishi Electric Corp 交差ゲート構造を持つ半導体装置およびその製造方法
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
WO2013095341A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
EP3127862B1 (en) 2015-08-06 2018-04-18 IMEC vzw A method of manufacturing a gate-all-around nanowire device comprising two different nanowires
US9570395B1 (en) 2015-11-17 2017-02-14 Samsung Electronics Co., Ltd. Semiconductor device having buried power rail
TWI739879B (zh) * 2016-08-10 2021-09-21 日商東京威力科創股份有限公司 用於半導體裝置的延伸區域
US9837414B1 (en) * 2016-10-31 2017-12-05 International Business Machines Corporation Stacked complementary FETs featuring vertically stacked horizontal nanowires
US10586765B2 (en) 2017-06-22 2020-03-10 Tokyo Electron Limited Buried power rails
US10546925B2 (en) * 2017-11-02 2020-01-28 International Business Machines Corporation Vertically stacked nFET and pFET with dual work function
US10236217B1 (en) * 2017-11-02 2019-03-19 International Business Machines Corporation Stacked field-effect transistors (FETs) with shared and non-shared gates
US10833078B2 (en) * 2017-12-04 2020-11-10 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
US11201152B2 (en) * 2018-04-20 2021-12-14 Globalfoundries Inc. Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor
US10490667B1 (en) * 2018-05-15 2019-11-26 International Business Machines Corporation Three-dimensional field effect device
US10707218B2 (en) * 2018-07-26 2020-07-07 Globalfoundries Inc. Two port SRAM cell using complementary nano-sheet/wire transistor devices
JP7351307B2 (ja) 2018-09-25 2023-09-27 株式会社ソシオネクスト 半導体装置及びその製造方法
US10741456B2 (en) * 2018-10-10 2020-08-11 International Business Machines Corporation Vertically stacked nanosheet CMOS transistor
US10734447B2 (en) * 2018-10-22 2020-08-04 International Business Machines Corporation Field-effect transistor unit cells for neural networks with differential weights
US10818674B2 (en) * 2019-03-07 2020-10-27 Globalfoundries Inc. Structures and SRAM bit cells integrating complementary field-effect transistors
WO2021138551A1 (en) * 2019-12-31 2021-07-08 Tokyo Electron Limited Cfet sram bit cell with three stacked device decks
US11239236B2 (en) 2020-03-23 2022-02-01 Intel Corporation Forksheet transistor architectures
US11626494B2 (en) * 2020-06-17 2023-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial backside contact

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190305104A1 (en) * 2018-04-02 2019-10-03 International Business Machines Corporation Nanosheet transistor with dual inner airgap spacers
US10424639B1 (en) * 2018-04-19 2019-09-24 International Business Machines Corporation Nanosheet transistor with high-mobility channel
US10510620B1 (en) * 2018-07-27 2019-12-17 GlobalFoundries, Inc. Work function metal patterning for N-P space between active nanostructures
US10559566B1 (en) * 2018-09-17 2020-02-11 International Business Machines Corporation Reduction of multi-threshold voltage patterning damage in nanosheet device structure

Also Published As

Publication number Publication date
JP7533575B2 (ja) 2024-08-14
CN115552604A (zh) 2022-12-30
US20230053433A1 (en) 2023-02-23
WO2021229740A1 (ja) 2021-11-18
US12543353B2 (en) 2026-02-03
JP7704265B2 (ja) 2025-07-08
JP2024147779A (ja) 2024-10-16
US20260090041A1 (en) 2026-03-26

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