JPWO2021157172A5 - - Google Patents
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- JPWO2021157172A5 JPWO2021157172A5 JP2021575626A JP2021575626A JPWO2021157172A5 JP WO2021157172 A5 JPWO2021157172 A5 JP WO2021157172A5 JP 2021575626 A JP2021575626 A JP 2021575626A JP 2021575626 A JP2021575626 A JP 2021575626A JP WO2021157172 A5 JPWO2021157172 A5 JP WO2021157172A5
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- product
- multiplexed signal
- real part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000034 method Methods 0.000 claims 1
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 8
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 8
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 6
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 4
- 240000006829 Ficus sundaica Species 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020018788 | 2020-02-06 | ||
| JP2020018788 | 2020-02-06 | ||
| PCT/JP2020/044792 WO2021157172A1 (ja) | 2020-02-06 | 2020-12-02 | 複素乗算回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2021157172A1 JPWO2021157172A1 (https=) | 2021-08-12 |
| JPWO2021157172A5 true JPWO2021157172A5 (https=) | 2022-08-17 |
| JP7317151B2 JP7317151B2 (ja) | 2023-07-28 |
Family
ID=77200456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021575626A Active JP7317151B2 (ja) | 2020-02-06 | 2020-12-02 | 複素乗算回路 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20230029006A1 (https=) |
| JP (1) | JP7317151B2 (https=) |
| WO (1) | WO2021157172A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12045612B2 (en) * | 2022-09-12 | 2024-07-23 | International Business Machines Corporation | Special-purpose digital-compute hardware for efficient element-wise aggregation, scaling and offset |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5752959A (en) * | 1980-09-11 | 1982-03-29 | Mitsubishi Electric Corp | Multiplier |
| KR100255868B1 (ko) * | 1997-06-28 | 2000-05-01 | 김영환 | 2의 보수 복소수 곱셈기 |
| EP1769391A1 (en) * | 2004-07-08 | 2007-04-04 | Asocs Ltd. | A method of and apparatus for implementing fast orthogonal transforms of variable size |
| US8572153B1 (en) * | 2004-12-16 | 2013-10-29 | Xilinx, Inc. | Multiplier circuit configurable for real or complex operation |
| US7797366B2 (en) * | 2006-02-15 | 2010-09-14 | Qualcomm Incorporated | Power-efficient sign extension for booth multiplication methods and systems |
| US8386553B1 (en) * | 2006-12-05 | 2013-02-26 | Altera Corporation | Large multiplier for programmable logic device |
| US8543635B2 (en) * | 2009-01-27 | 2013-09-24 | Xilinx, Inc. | Digital signal processing block with preadder stage |
-
2020
- 2020-12-02 WO PCT/JP2020/044792 patent/WO2021157172A1/ja not_active Ceased
- 2020-12-02 US US17/790,833 patent/US20230029006A1/en active Pending
- 2020-12-02 JP JP2021575626A patent/JP7317151B2/ja active Active
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