JP7317151B2 - 複素乗算回路 - Google Patents

複素乗算回路 Download PDF

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Publication number
JP7317151B2
JP7317151B2 JP2021575626A JP2021575626A JP7317151B2 JP 7317151 B2 JP7317151 B2 JP 7317151B2 JP 2021575626 A JP2021575626 A JP 2021575626A JP 2021575626 A JP2021575626 A JP 2021575626A JP 7317151 B2 JP7317151 B2 JP 7317151B2
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signal
circuit
multiplexed signal
product
real part
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Japanese (ja)
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JPWO2021157172A1 (https=
JPWO2021157172A5 (https=
Inventor
英幸 天谷
紀俊 川口
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G06F7/4812—Complex multiplication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • Complex Calculations (AREA)
  • Time-Division Multiplex Systems (AREA)
JP2021575626A 2020-02-06 2020-12-02 複素乗算回路 Active JP7317151B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020018788 2020-02-06
JP2020018788 2020-02-06
PCT/JP2020/044792 WO2021157172A1 (ja) 2020-02-06 2020-12-02 複素乗算回路

Publications (3)

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JPWO2021157172A1 JPWO2021157172A1 (https=) 2021-08-12
JPWO2021157172A5 JPWO2021157172A5 (https=) 2022-08-17
JP7317151B2 true JP7317151B2 (ja) 2023-07-28

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JP2021575626A Active JP7317151B2 (ja) 2020-02-06 2020-12-02 複素乗算回路

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US (1) US20230029006A1 (https=)
JP (1) JP7317151B2 (https=)
WO (1) WO2021157172A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12045612B2 (en) * 2022-09-12 2024-07-23 International Business Machines Corporation Special-purpose digital-compute hardware for efficient element-wise aggregation, scaling and offset

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008506191A (ja) 2004-07-08 2008-02-28 アソクス リミテッド 可変サイズの高速直交変換を実施する方法および機器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752959A (en) * 1980-09-11 1982-03-29 Mitsubishi Electric Corp Multiplier
KR100255868B1 (ko) * 1997-06-28 2000-05-01 김영환 2의 보수 복소수 곱셈기
US8572153B1 (en) * 2004-12-16 2013-10-29 Xilinx, Inc. Multiplier circuit configurable for real or complex operation
US7797366B2 (en) * 2006-02-15 2010-09-14 Qualcomm Incorporated Power-efficient sign extension for booth multiplication methods and systems
US8386553B1 (en) * 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US8543635B2 (en) * 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008506191A (ja) 2004-07-08 2008-02-28 アソクス リミテッド 可変サイズの高速直交変換を実施する方法および機器

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US20230029006A1 (en) 2023-01-26
WO2021157172A1 (ja) 2021-08-12
JPWO2021157172A1 (https=) 2021-08-12

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