JP2024537610A5 - - Google Patents
Info
- Publication number
- JP2024537610A5 JP2024537610A5 JP2024513244A JP2024513244A JP2024537610A5 JP 2024537610 A5 JP2024537610 A5 JP 2024537610A5 JP 2024513244 A JP2024513244 A JP 2024513244A JP 2024513244 A JP2024513244 A JP 2024513244A JP 2024537610 A5 JP2024537610 A5 JP 2024537610A5
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- tap
- circuit
- output
- sequentially connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/465,550 | 2021-09-02 | ||
| US17/465,550 US20230065725A1 (en) | 2021-09-02 | 2021-09-02 | Parallel depth-wise processing architectures for neural networks |
| PCT/US2022/075255 WO2023034696A1 (en) | 2021-09-02 | 2022-08-22 | Parallel depth-wise processing architectures for neural networks |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2024537610A JP2024537610A (ja) | 2024-10-16 |
| JP2024537610A5 true JP2024537610A5 (https=) | 2025-08-18 |
Family
ID=83506452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024513244A Pending JP2024537610A (ja) | 2021-09-02 | 2022-08-22 | ニューラルネットワークに関する並列深さ単位処理アーキテクチャ |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20230065725A1 (https=) |
| EP (1) | EP4396726B1 (https=) |
| JP (1) | JP2024537610A (https=) |
| KR (1) | KR20240058084A (https=) |
| CN (1) | CN117897708A (https=) |
| TW (1) | TW202316325A (https=) |
| WO (1) | WO2023034696A1 (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12340304B2 (en) * | 2021-08-10 | 2025-06-24 | Qualcomm Incorporated | Partial sum management and reconfigurable systolic flow architectures for in-memory computation |
| KR102706004B1 (ko) * | 2021-12-21 | 2024-09-12 | 주식회사 넥스트칩 | 차량을 제어하기 위한 이미지 처리 방법 및 그 방법을 수행하는 전자 장치 |
| KR20230123864A (ko) * | 2022-02-17 | 2023-08-24 | 주식회사 마키나락스 | 인공지능 기반의 반도체 설계 방법 |
| KR20250041871A (ko) * | 2023-09-19 | 2025-03-26 | 주식회사 딥엑스 | 가변 주파수를 이용하여 신경 프로세싱 유닛의 파워를 낮추는 기술 |
| TWI884084B (zh) * | 2024-09-16 | 2025-05-11 | 國立陽明交通大學 | 記憶體內運算(cim)裝置及其縮放係數的訓練方法 |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7196708B2 (en) * | 2004-03-31 | 2007-03-27 | Sony Corporation | Parallel vector processing |
| US20050226337A1 (en) * | 2004-03-31 | 2005-10-13 | Mikhail Dorojevets | 2D block processing architecture |
| JP2010192983A (ja) * | 2009-02-16 | 2010-09-02 | Renesas Electronics Corp | フィルタ処理装置及び半導体装置 |
| US8583720B2 (en) * | 2010-02-10 | 2013-11-12 | L3 Communications Integrated Systems, L.P. | Reconfigurable networked processing elements partial differential equations system |
| US20180164866A1 (en) * | 2016-12-13 | 2018-06-14 | Qualcomm Incorporated | Low-power architecture for sparse neural network |
| KR102642853B1 (ko) * | 2017-01-05 | 2024-03-05 | 한국전자통신연구원 | 컨볼루션 회로, 그것을 포함하는 어플리케이션 프로세서 및 그것의 동작 방법 |
| US11507429B2 (en) * | 2017-09-14 | 2022-11-22 | Electronics And Telecommunications Research Institute | Neural network accelerator including bidirectional processing element array |
| US10872290B2 (en) * | 2017-09-21 | 2020-12-22 | Raytheon Company | Neural network processor with direct memory access and hardware acceleration circuits |
| US10768856B1 (en) * | 2018-03-12 | 2020-09-08 | Amazon Technologies, Inc. | Memory access for multiple circuit components |
| US11475306B2 (en) * | 2018-03-22 | 2022-10-18 | Amazon Technologies, Inc. | Processing for multiple input data sets |
| US12175356B2 (en) * | 2018-05-15 | 2024-12-24 | Mitsubishi Electric Corporation | Arithmetic device |
| US11347916B1 (en) * | 2019-06-28 | 2022-05-31 | Amazon Technologies, Inc. | Increasing positive clock skew for systolic array critical path |
| US20210012186A1 (en) * | 2019-07-11 | 2021-01-14 | Facebook Technologies, Llc | Systems and methods for pipelined parallelism to accelerate distributed processing |
| US11842169B1 (en) * | 2019-09-25 | 2023-12-12 | Amazon Technologies, Inc. | Systolic multiply delayed accumulate processor architecture |
| US11816446B2 (en) * | 2019-11-27 | 2023-11-14 | Amazon Technologies, Inc. | Systolic array component combining multiple integer and floating-point data types |
| US11422773B1 (en) * | 2020-06-29 | 2022-08-23 | Amazon Technologies, Inc. | Multiple busses within a systolic array processing element |
| US11308026B1 (en) * | 2020-06-29 | 2022-04-19 | Amazon Technologies, Inc. | Multiple busses interleaved in a systolic array |
| US11308027B1 (en) * | 2020-06-29 | 2022-04-19 | Amazon Technologies, Inc. | Multiple accumulate busses in a systolic array |
| US20220383081A1 (en) * | 2021-05-28 | 2022-12-01 | Meta Platforms Technologies, Llc | Bandwidth-aware flexible-scheduling machine learning accelerator |
| US11880682B2 (en) * | 2021-06-30 | 2024-01-23 | Amazon Technologies, Inc. | Systolic array with efficient input reduction and extended array performance |
| US11494627B1 (en) * | 2021-07-08 | 2022-11-08 | Hong Kong Applied Science and Technology Research Institute Company Limited | Dynamic tile parallel neural network accelerator |
-
2021
- 2021-09-02 US US17/465,550 patent/US20230065725A1/en active Pending
-
2022
- 2022-08-22 WO PCT/US2022/075255 patent/WO2023034696A1/en not_active Ceased
- 2022-08-22 KR KR1020247006183A patent/KR20240058084A/ko active Pending
- 2022-08-22 EP EP22782631.0A patent/EP4396726B1/en active Active
- 2022-08-22 CN CN202280058042.3A patent/CN117897708A/zh active Pending
- 2022-08-22 JP JP2024513244A patent/JP2024537610A/ja active Pending
- 2022-08-23 TW TW111131684A patent/TW202316325A/zh unknown
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2024537610A5 (https=) | ||
| Saokar et al. | High speed signed multiplier for digital signal processing applications | |
| JP2011034566A5 (https=) | ||
| WO1999038088A1 (en) | Method and apparatus for arithmetic operation | |
| CN109144469B (zh) | 流水线结构神经网络矩阵运算架构及方法 | |
| CN103942028A (zh) | 应用在密码技术中的大整数乘法运算方法及装置 | |
| CN100583023C (zh) | 组合多项式和自然乘法的乘法器架构 | |
| JP2021517301A5 (https=) | ||
| CN108762719B (zh) | 一种并行广义内积重构控制器 | |
| Dinesh et al. | Comparison of regular and tree based multiplier architectures with modified booth encoding for 4 bits on layout level using 45nm technology | |
| WO2013042249A1 (ja) | 高速フーリエ変換回路 | |
| US6304133B1 (en) | Moving average filter | |
| CN113556101B (zh) | Iir滤波器及其数据处理方法 | |
| Hussain et al. | A Fast and Reduced Complexity Wallace Multiplier. | |
| CN102184160B (zh) | 基于余数系统的快速傅立叶变换系统 | |
| RU2717915C1 (ru) | Вычислительное устройство | |
| Ande et al. | High-speed vedic multiplier implementation using memristive and speculative adders | |
| WO2012163121A1 (zh) | 数字滤波方法和装置 | |
| JP5102710B2 (ja) | デジタルフィルタ | |
| Kamal et al. | Efficient VLSI architecture for FIR filter using DA-RNS | |
| CN120956406B (zh) | 加法电路、运算电路、执行哈希算法的电路及相关装置 | |
| RU2838847C1 (ru) | Конвейерный умножитель по модулям | |
| JPS59194242A (ja) | ディジタル乗算累積加算装置 | |
| Zhou et al. | New algorithm and fast VLSI implementation for modular inversion in galois field GF (p) | |
| KR100386979B1 (ko) | 갈로아체상에서 비트 직렬 승산기의 병렬화 방법 및 이를이용한 직병렬 승산기 |