JP2021517301A5 - - Google Patents

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Publication number
JP2021517301A5
JP2021517301A5 JP2020546908A JP2020546908A JP2021517301A5 JP 2021517301 A5 JP2021517301 A5 JP 2021517301A5 JP 2020546908 A JP2020546908 A JP 2020546908A JP 2020546908 A JP2020546908 A JP 2020546908A JP 2021517301 A5 JP2021517301 A5 JP 2021517301A5
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JP
Japan
Prior art keywords
csa
input
carry
logic
adder
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JP2020546908A
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English (en)
Japanese (ja)
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JP2021517301A (ja
JP7292297B2 (ja
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Priority claimed from US15/933,229 external-priority patent/US10628124B2/en
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Publication of JP7292297B2 publication Critical patent/JP7292297B2/ja
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JP2020546908A 2018-03-22 2019-03-18 確率的丸めロジック Active JP7292297B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/933,229 2018-03-22
US15/933,229 US10628124B2 (en) 2018-03-22 2018-03-22 Stochastic rounding logic
PCT/US2019/022685 WO2019182943A1 (en) 2018-03-22 2019-03-18 Stochastic rounding logic

Publications (3)

Publication Number Publication Date
JP2021517301A JP2021517301A (ja) 2021-07-15
JP2021517301A5 true JP2021517301A5 (https=) 2022-03-23
JP7292297B2 JP7292297B2 (ja) 2023-06-16

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ID=65952226

Family Applications (1)

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JP2020546908A Active JP7292297B2 (ja) 2018-03-22 2019-03-18 確率的丸めロジック

Country Status (6)

Country Link
US (1) US10628124B2 (https=)
EP (1) EP3769208B1 (https=)
JP (1) JP7292297B2 (https=)
KR (1) KR102697307B1 (https=)
CN (1) CN111936965B (https=)
WO (1) WO2019182943A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108256644B (zh) * 2018-01-05 2021-06-22 上海兆芯集成电路有限公司 微处理器电路以及执行神经网络运算的方法
US10908878B2 (en) * 2018-11-26 2021-02-02 Nvidia Corporation Dynamic directional rounding
US11132198B2 (en) * 2019-08-29 2021-09-28 International Business Machines Corporation Instruction handling for accumulation of register results in a microprocessor
US11615782B2 (en) * 2020-11-12 2023-03-28 Sony Interactive Entertainment Inc. Semi-sorted batching with variable length input for efficient training
CN113791756B (zh) * 2021-09-18 2022-12-23 中科寒武纪科技股份有限公司 转数方法、存储介质、装置及板卡
CN113835677A (zh) * 2021-09-23 2021-12-24 龙芯中科技术股份有限公司 操作数处理系统、方法及处理器

Family Cites Families (14)

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Publication number Priority date Publication date Assignee Title
US5974435A (en) * 1997-08-28 1999-10-26 Malleable Technologies, Inc. Reconfigurable arithmetic datapath
US20040078401A1 (en) 2002-10-22 2004-04-22 Hilton Howard E. Bias-free rounding in digital signal processing
CN100350389C (zh) * 2003-10-24 2007-11-21 英特尔公司 用于检测软错误的方法、设备和处理器
US8019805B1 (en) 2003-12-09 2011-09-13 Globalfoundries Inc. Apparatus and method for multiple pass extended precision floating point multiplication
JP4544870B2 (ja) 2004-01-26 2010-09-15 富士通セミコンダクター株式会社 演算回路装置
US8266198B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8239441B2 (en) * 2008-05-15 2012-08-07 Oracle America, Inc. Leading zero estimation modification for unfused rounding catastrophic cancellation
US8533250B1 (en) * 2009-06-17 2013-09-10 Altera Corporation Multiplier with built-in accumulator
US9710228B2 (en) * 2014-12-29 2017-07-18 Imagination Technologies Limited Unified multiply unit
US10108397B2 (en) * 2015-08-25 2018-10-23 Samsung Electronics Co., Ltd. Fast close path solution for a three-path fused multiply-add design
US10552370B2 (en) 2015-10-08 2020-02-04 Via Alliance Semiconductor Co., Ltd. Neural network unit with output buffer feedback for performing recurrent neural network computations
US9940102B2 (en) * 2016-01-04 2018-04-10 International Business Machines Corporation Partial stochastic rounding that includes sticky and guard bits
US10489152B2 (en) 2016-01-28 2019-11-26 International Business Machines Corporation Stochastic rounding floating-point add instruction using entropy from a register
US9952829B2 (en) * 2016-02-01 2018-04-24 International Business Machines Corporation Binary fused multiply-add floating-point calculations

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