CN111936965B - 随机舍入逻辑 - Google Patents

随机舍入逻辑 Download PDF

Info

Publication number
CN111936965B
CN111936965B CN201980021078.2A CN201980021078A CN111936965B CN 111936965 B CN111936965 B CN 111936965B CN 201980021078 A CN201980021078 A CN 201980021078A CN 111936965 B CN111936965 B CN 111936965B
Authority
CN
China
Prior art keywords
csa
input
carry
output
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980021078.2A
Other languages
English (en)
Chinese (zh)
Other versions
CN111936965A (zh
Inventor
加布里埃尔·H·洛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN111936965A publication Critical patent/CN111936965A/zh
Application granted granted Critical
Publication of CN111936965B publication Critical patent/CN111936965B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • Artificial Intelligence (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
CN201980021078.2A 2018-03-22 2019-03-18 随机舍入逻辑 Active CN111936965B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/933,229 2018-03-22
US15/933,229 US10628124B2 (en) 2018-03-22 2018-03-22 Stochastic rounding logic
PCT/US2019/022685 WO2019182943A1 (en) 2018-03-22 2019-03-18 Stochastic rounding logic

Publications (2)

Publication Number Publication Date
CN111936965A CN111936965A (zh) 2020-11-13
CN111936965B true CN111936965B (zh) 2025-03-21

Family

ID=65952226

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980021078.2A Active CN111936965B (zh) 2018-03-22 2019-03-18 随机舍入逻辑

Country Status (6)

Country Link
US (1) US10628124B2 (https=)
EP (1) EP3769208B1 (https=)
JP (1) JP7292297B2 (https=)
KR (1) KR102697307B1 (https=)
CN (1) CN111936965B (https=)
WO (1) WO2019182943A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108256644B (zh) * 2018-01-05 2021-06-22 上海兆芯集成电路有限公司 微处理器电路以及执行神经网络运算的方法
US10908878B2 (en) * 2018-11-26 2021-02-02 Nvidia Corporation Dynamic directional rounding
US11132198B2 (en) * 2019-08-29 2021-09-28 International Business Machines Corporation Instruction handling for accumulation of register results in a microprocessor
US11615782B2 (en) * 2020-11-12 2023-03-28 Sony Interactive Entertainment Inc. Semi-sorted batching with variable length input for efficient training
CN113791756B (zh) * 2021-09-18 2022-12-23 中科寒武纪科技股份有限公司 转数方法、存储介质、装置及板卡
CN113835677A (zh) * 2021-09-23 2021-12-24 龙芯中科技术股份有限公司 操作数处理系统、方法及处理器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5974435A (en) * 1997-08-28 1999-10-26 Malleable Technologies, Inc. Reconfigurable arithmetic datapath
US20040078401A1 (en) 2002-10-22 2004-04-22 Hilton Howard E. Bias-free rounding in digital signal processing
CN100350389C (zh) * 2003-10-24 2007-11-21 英特尔公司 用于检测软错误的方法、设备和处理器
US8019805B1 (en) 2003-12-09 2011-09-13 Globalfoundries Inc. Apparatus and method for multiple pass extended precision floating point multiplication
JP4544870B2 (ja) 2004-01-26 2010-09-15 富士通セミコンダクター株式会社 演算回路装置
US8266198B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8239441B2 (en) * 2008-05-15 2012-08-07 Oracle America, Inc. Leading zero estimation modification for unfused rounding catastrophic cancellation
US8533250B1 (en) * 2009-06-17 2013-09-10 Altera Corporation Multiplier with built-in accumulator
US9710228B2 (en) * 2014-12-29 2017-07-18 Imagination Technologies Limited Unified multiply unit
US10108397B2 (en) * 2015-08-25 2018-10-23 Samsung Electronics Co., Ltd. Fast close path solution for a three-path fused multiply-add design
US10552370B2 (en) 2015-10-08 2020-02-04 Via Alliance Semiconductor Co., Ltd. Neural network unit with output buffer feedback for performing recurrent neural network computations
US9940102B2 (en) * 2016-01-04 2018-04-10 International Business Machines Corporation Partial stochastic rounding that includes sticky and guard bits
US10489152B2 (en) 2016-01-28 2019-11-26 International Business Machines Corporation Stochastic rounding floating-point add instruction using entropy from a register
US9952829B2 (en) * 2016-02-01 2018-04-24 International Business Machines Corporation Binary fused multiply-add floating-point calculations

Also Published As

Publication number Publication date
CN111936965A (zh) 2020-11-13
JP2021517301A (ja) 2021-07-15
US10628124B2 (en) 2020-04-21
WO2019182943A1 (en) 2019-09-26
US20190294412A1 (en) 2019-09-26
JP7292297B2 (ja) 2023-06-16
EP3769208A1 (en) 2021-01-27
EP3769208B1 (en) 2022-10-26
KR102697307B1 (ko) 2024-08-23
KR20200134281A (ko) 2020-12-01

Similar Documents

Publication Publication Date Title
CN111936965B (zh) 随机舍入逻辑
US11169778B2 (en) Converting floating point numbers to reduce the precision
Moss et al. A two-speed, radix-4, serial–parallel multiplier
Demmel et al. Parallel reproducible summation
JP3244506B2 (ja) 小型乗算器
CN113168310B (zh) 用于转换数字的硬件模块
KR20190044550A (ko) 신경망에서의 무작위성 생성
US20160224318A1 (en) Method and apparatus for converting from integer to floating point representation
CN101295237B (zh) 求商和余数的高速除法器
KR100818011B1 (ko) 연산 처리 장치, 정보 처리 장치, 및 연산 처리 방법
US7219117B2 (en) Methods and systems for computing floating-point intervals
US7236999B2 (en) Methods and systems for computing the quotient of floating-point intervals
KR20240095009A (ko) 시프트 마지막 곱셈 및 누산(mac) 프로세스를 위한 시스템 및 방법
JP2018097864A (ja) リーディングゼロ予想
Sravya et al. Hardware posit numeration system primarily based on arithmetic operations
US20090327388A1 (en) Static logic ling adder
CN1178588A (zh) 使用移位装置的求幂电路及其使用方法
TWI753668B (zh) 資訊處理裝置、電腦程式、記錄媒體及資訊處理方法
Zhao Design and application analysis of arithmetic logic unit in digital systems
Hsiao Power-and Area-Efficient Techniques and Methodologies for Emerging Circuit Design
Abraham et al. An ASIC design of an optimized multiplication using twin precision
Alexandridis et al. Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines
JP3471577B2 (ja) ビット連続数検出装置
Chen et al. Low-area and high-speed approximate matrix-vector multiplier
Karthick et al. VLSI Implementation of Multipliers for Artificial Intelligence Applications: A Survey

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant