TW202316325A - 用於神經網路的並行逐深度處理架構 - Google Patents

用於神經網路的並行逐深度處理架構 Download PDF

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TW202316325A
TW202316325A TW111131684A TW111131684A TW202316325A TW 202316325 A TW202316325 A TW 202316325A TW 111131684 A TW111131684 A TW 111131684A TW 111131684 A TW111131684 A TW 111131684A TW 202316325 A TW202316325 A TW 202316325A
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默斯塔法 貝達羅格魯
中澤 王
弗朗索瓦伊布拉欣 阿塔拉
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美商高通公司
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TW111131684A 2021-09-02 2022-08-23 用於神經網路的並行逐深度處理架構 TW202316325A (zh)

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US17/465,550 2021-09-02
US17/465,550 US20230065725A1 (en) 2021-09-02 2021-09-02 Parallel depth-wise processing architectures for neural networks

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US (1) US20230065725A1 (https=)
EP (1) EP4396726B1 (https=)
JP (1) JP2024537610A (https=)
KR (1) KR20240058084A (https=)
CN (1) CN117897708A (https=)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI884084B (zh) * 2024-09-16 2025-05-11 國立陽明交通大學 記憶體內運算(cim)裝置及其縮放係數的訓練方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12340304B2 (en) * 2021-08-10 2025-06-24 Qualcomm Incorporated Partial sum management and reconfigurable systolic flow architectures for in-memory computation
KR102706004B1 (ko) * 2021-12-21 2024-09-12 주식회사 넥스트칩 차량을 제어하기 위한 이미지 처리 방법 및 그 방법을 수행하는 전자 장치
KR20230123864A (ko) * 2022-02-17 2023-08-24 주식회사 마키나락스 인공지능 기반의 반도체 설계 방법
KR20250041871A (ko) * 2023-09-19 2025-03-26 주식회사 딥엑스 가변 주파수를 이용하여 신경 프로세싱 유닛의 파워를 낮추는 기술

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196708B2 (en) * 2004-03-31 2007-03-27 Sony Corporation Parallel vector processing
US20050226337A1 (en) * 2004-03-31 2005-10-13 Mikhail Dorojevets 2D block processing architecture
JP2010192983A (ja) * 2009-02-16 2010-09-02 Renesas Electronics Corp フィルタ処理装置及び半導体装置
US8583720B2 (en) * 2010-02-10 2013-11-12 L3 Communications Integrated Systems, L.P. Reconfigurable networked processing elements partial differential equations system
US20180164866A1 (en) * 2016-12-13 2018-06-14 Qualcomm Incorporated Low-power architecture for sparse neural network
KR102642853B1 (ko) * 2017-01-05 2024-03-05 한국전자통신연구원 컨볼루션 회로, 그것을 포함하는 어플리케이션 프로세서 및 그것의 동작 방법
US11507429B2 (en) * 2017-09-14 2022-11-22 Electronics And Telecommunications Research Institute Neural network accelerator including bidirectional processing element array
US10872290B2 (en) * 2017-09-21 2020-12-22 Raytheon Company Neural network processor with direct memory access and hardware acceleration circuits
US10768856B1 (en) * 2018-03-12 2020-09-08 Amazon Technologies, Inc. Memory access for multiple circuit components
US11475306B2 (en) * 2018-03-22 2022-10-18 Amazon Technologies, Inc. Processing for multiple input data sets
US12175356B2 (en) * 2018-05-15 2024-12-24 Mitsubishi Electric Corporation Arithmetic device
US11347916B1 (en) * 2019-06-28 2022-05-31 Amazon Technologies, Inc. Increasing positive clock skew for systolic array critical path
US20210012186A1 (en) * 2019-07-11 2021-01-14 Facebook Technologies, Llc Systems and methods for pipelined parallelism to accelerate distributed processing
US11842169B1 (en) * 2019-09-25 2023-12-12 Amazon Technologies, Inc. Systolic multiply delayed accumulate processor architecture
US11816446B2 (en) * 2019-11-27 2023-11-14 Amazon Technologies, Inc. Systolic array component combining multiple integer and floating-point data types
US11422773B1 (en) * 2020-06-29 2022-08-23 Amazon Technologies, Inc. Multiple busses within a systolic array processing element
US11308026B1 (en) * 2020-06-29 2022-04-19 Amazon Technologies, Inc. Multiple busses interleaved in a systolic array
US11308027B1 (en) * 2020-06-29 2022-04-19 Amazon Technologies, Inc. Multiple accumulate busses in a systolic array
US20220383081A1 (en) * 2021-05-28 2022-12-01 Meta Platforms Technologies, Llc Bandwidth-aware flexible-scheduling machine learning accelerator
US11880682B2 (en) * 2021-06-30 2024-01-23 Amazon Technologies, Inc. Systolic array with efficient input reduction and extended array performance
US11494627B1 (en) * 2021-07-08 2022-11-08 Hong Kong Applied Science and Technology Research Institute Company Limited Dynamic tile parallel neural network accelerator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI884084B (zh) * 2024-09-16 2025-05-11 國立陽明交通大學 記憶體內運算(cim)裝置及其縮放係數的訓練方法

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JP2024537610A (ja) 2024-10-16
KR20240058084A (ko) 2024-05-03
US20230065725A1 (en) 2023-03-02
EP4396726A1 (en) 2024-07-10
EP4396726B1 (en) 2026-04-22
CN117897708A (zh) 2024-04-16

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