JPWO2020194432A1 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 150000002500 ions Chemical class 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005468 ion implantation Methods 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 30
- 230000001066 destructive effect Effects 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
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- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 24
- 238000010586 diagram Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
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- 238000002347 injection Methods 0.000 description 3
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
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- 230000001070 adhesive effect Effects 0.000 description 1
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- 239000002344 surface layer Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
Description
図1は実施の形態1に係る半導体装置10の図である。半導体装置10は半導体基板12を備える。半導体基板12はGaAs、GaN、SiCまたはSiなどからなる。
図3は実施の形態2に係る半導体装置30の図である。半導体装置30は実施の形態1に係る半導体装置10と同様だが、配線36の側面にもイオン注入層36aが形成されている点が異なる。
図5は実施の形態3に係る半導体装置50の図である。半導体装置50は実施の形態1に係る半導体装置10と同様だが、配線56および絶縁膜54に注入されたイオンの鉛直方向における分布が異なる。
図8は実施の形態4に係る半導体装置70の図である。半導体装置70は実施の形態2に係る半導体装置30と同様だが、絶縁膜74の上面にイオン注入層がない点と、イオン注入されたイオン種の限定が異なる。イオン種は、絶縁膜14に注入されても絶縁性を損なわないAr、Nなどに加え、B、Si、Pd、Ti、Ta、AlまたはCoなど、イオン注入されると絶縁膜の電気伝導度が高くなるものを用いてもよい。これらのイオン種は後述するようにAuでできた配線に注入され、Auに対して不純物として働くため、これらのイオンの元となる元素をここでは不純物元素と呼ぶ。イオン注入層76a中の不純物元素の濃度は1×1017cm−3以上1×1021cm−3以下である。
12,112 半導体基板
14,54,74 絶縁膜
14a,14a,54a,82a,112a イオン注入層
16,36,56,76,116 配線
16a,36a,56a,76a,116a イオン注入層
18,18,58,78,118 絶縁膜
82 レジスト
Claims (12)
- 半導体基板の上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の上に少なくとも最上層がAuでできた配線を形成する工程と、
前記配線の上面および前記第1の絶縁膜の上面のうち前記配線に覆われていない領域に、前記絶縁膜に注入されても絶縁性を損なわないイオンを注入する工程と、
前記配線を覆う第2の絶縁膜を形成する工程とをこの順に備える半導体装置の製造方法。 - 半導体基板の上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の上に少なくとも最上層がAuでできた配線を形成する工程と、
前記配線を覆う第2の絶縁膜を形成する工程と、
前記配線の上面および前記第1の絶縁膜の上面のうち前記配線に覆われていない領域に、前記絶縁膜に注入されても絶縁性を損なわないイオンを注入する工程と、
前記配線および前記第2の絶縁膜に注入された前記イオンの分布のピークがそれぞれ、前記配線の上面と前記第2の絶縁膜の界面付近にある半導体装置の製造方法。 - 前記イオンはArまたはNである請求項1または2に記載の半導体装置の製造方法。
- 前記配線の側面の少なくとも上部がAuでできており、
前記イオンを注入する方法として斜めイオン注入法を用い、前記配線の側面にも前記イオンを注入する請求項1〜3のいずれか1項に記載の半導体装置の製造方法。 - 半導体基板の上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の上に少なくとも最上層および側面の少なくとも上部がAuでできた配線を形成する工程と、
前記第1の絶縁膜の上面のうち前記配線に覆われていない領域にレジストを形成する工程と、
前記レジストを熱処理で変形させ、前記配線の側面のうち前記レジストと接触する領域の少なくとも一部を露出させる工程と、
前記配線の上面、前記配線の側面の少なくとも上部および前記レジストの上面に斜めイオン注入法を用いてイオンを注入する工程と、
前記レジストを除去する工程と、
前記配線を覆う第2の絶縁膜を形成する工程とをこの順に備える半導体装置の製造方法。 - 前記イオンはB、Si、Pd、Ti、Ta、Al、Co、ArまたはNのいずれか1つである請求項5に記載の半導体装置の製造方法。
- 半導体基板と、
前記半導体基板の上の第1の絶縁膜と
前記第1の絶縁膜の上の少なくとも最上層がAuでできた配線と、
前記配線を覆う第2の絶縁膜とを備え、
前記配線の上面付近および前記第1の絶縁膜の上面のうち前記配線に覆われていない領域付近に、絶縁性非破壊元素が1×1017cm−3以上1×1021cm−3以下の濃度で存在する半導体装置。 - 前記絶縁性非破壊元素が前記第2の絶縁膜の下面付近にも存在し、
前記配線の上面および前記配線の上面と接する前記第2の絶縁膜の下面における前記絶縁性非破壊元素の分布のピークがそれぞれ、前記配線の上面と前記第2の絶縁膜の界面付近にある請求項7に記載の半導体装置。 - 前記絶縁性非破壊元素はArまたはNである請求項7または8に記載の半導体装置。
- 前記配線の側面の少なくとも上部がAuでできており、
前記絶縁性非破壊元素が前記配線の側面付近にも1×1017cm−3以上1×1021cm−3以下の濃度で存在する請求項7〜9のいずれか1項に記載の半導体装置。 - 半導体基板と、
前記半導体基板の上の第1の絶縁膜と
前記第1の絶縁膜の上の少なくとも最上層および側面の少なくとも上部がAuでできた配線と、
前記配線を覆う第2の絶縁膜とを備え、
前記配線の上面付近および側面付近に不純物元素が1×1017cm−3以上1×1021cm−3以下の濃度で存在する半導体装置。 - 前記不純物元素はB、Si、Pd、Ti、Ta、Al、Co、ArまたはNのいずれか1つである請求項11に記載の半導体装置。
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- 2019-03-25 CN CN201980089197.1A patent/CN113574636A/zh active Pending
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JPH05109721A (ja) * | 1991-10-15 | 1993-04-30 | Nec Corp | 半導体集積回路 |
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