WO2020194432A1 - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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WO2020194432A1
WO2020194432A1 PCT/JP2019/012435 JP2019012435W WO2020194432A1 WO 2020194432 A1 WO2020194432 A1 WO 2020194432A1 JP 2019012435 W JP2019012435 W JP 2019012435W WO 2020194432 A1 WO2020194432 A1 WO 2020194432A1
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Prior art keywords
wiring
insulating film
semiconductor device
insulating
manufacturing
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PCT/JP2019/012435
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English (en)
French (fr)
Inventor
浩平 西口
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三菱電機株式会社
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Priority to CN201980089197.1A priority Critical patent/CN113574636A/zh
Priority to DE112019007079.7T priority patent/DE112019007079B4/de
Priority to JP2021508409A priority patent/JP7004111B2/ja
Priority to US17/294,299 priority patent/US11335594B2/en
Priority to PCT/JP2019/012435 priority patent/WO2020194432A1/ja
Publication of WO2020194432A1 publication Critical patent/WO2020194432A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device in which wiring made of Au is covered with an insulating film, and a semiconductor device.
  • Au which has excellent reliability, is used as the material for wiring the transistors.
  • the wiring is covered with an insulating film (for example, SiO or SiN) for the purpose of protecting the device.
  • an insulating film for example, SiO or SiN
  • Au is chemically stable, when an insulating film is formed on Au, there is a problem that the adhesive force between Au and the insulating film is weak and the insulating film on the wiring is easily peeled off.
  • the present invention has been made to solve the above-mentioned problems, and an object of the present invention is a method for manufacturing a semiconductor device that achieves both improvement of adhesion between a wiring made of Au and an insulating film on the wiring and suppression of an increase in the number of manufacturing steps. And to obtain semiconductor devices.
  • the method for manufacturing a semiconductor device includes a step of forming a first insulating film on a semiconductor substrate and a step of forming a wiring having at least the uppermost layer made of Au on the first insulating film.
  • a step of injecting ions that do not impair the insulating property even if injected into the insulating film and a second insulating film that covers the wiring are applied to the upper surface of the wiring and the upper surface of the first insulating film that are not covered by the wiring.
  • a step of forming is provided in this order.
  • the semiconductor device includes a semiconductor substrate, a second insulating film on the semiconductor substrate, a wiring in which at least the uppermost layer on the first insulating film is made of Au, and a second insulation covering the wiring.
  • Insulating non-destructive elements are 1 ⁇ 10 17 cm -3 or more 1 ⁇ 10 21 cm -3 in the vicinity of the upper surface of the wiring and the area of the upper surface of the first insulating film that is not covered by the wiring. It exists in the following concentrations.
  • the wiring made of Au since ions that do not impair the insulating property even when injected into the insulating film under the wiring are injected onto the upper surface of the wiring made of Au, the wiring made of Au. It is possible to improve the adhesion between the wiring and the insulating film on the wiring and suppress the increase in the number of manufacturing processes.
  • FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 2.
  • FIG. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2.
  • FIG. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3.
  • FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 4.
  • FIG. 1 is a diagram of the semiconductor device 10 according to the first embodiment.
  • the semiconductor device 10 includes a semiconductor substrate 12.
  • the semiconductor substrate 12 is made of GaAs, GaN, SiC, Si, or the like.
  • the insulating film 14 is formed on the semiconductor substrate 12.
  • the insulating film 14 is made of polyimide, BCB (benzocyclobutene), CVD (Chemical Vapor Deposition) film or the like.
  • the CVD film is an insulating film such as SiO or SiN formed by the CVD method.
  • Wiring 16 is formed on the insulating film 14.
  • the wiring 16 is formed of Au on a substrate such as Ti, Ta, Cr, Ti / Pt or TiW.
  • Ti / Pt is a structure in which Pt is formed on Ti
  • TiW is an alloy of Ti and W. Since the wiring 16 is formed of Au on the base, at least the uppermost layer of the wiring 16 is made of Au. Further, since the side surface of the wiring 16 above the base is made of Au, at least the upper part of the side surface of the wiring 16 is made of Au. Since the base is thinner than Au, it is omitted in the figure.
  • An ion implantation layer 16a in which ions are implanted is formed on the upper surface of the wiring 16.
  • the ionic species is an element that does not impair the insulating property even when injected into the insulating film 14, and is referred to here as an insulating non-destructive element.
  • the insulating non-destructive element is specifically Ar or N.
  • An ion implantation layer 14a is also formed in a region of the upper surface of the insulating film 14 that is not covered by the wiring 16.
  • the concentration of the insulating non-destructive element in the ion-implanted layer 16a and the ion-implanted layer 14a is 1 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 21 cm -3 or less.
  • An insulating film 18 is formed so as to cover the wiring 16.
  • the insulating film 18 is SiO, SiN, SiON, AlO, TaO, or the like.
  • the insulating film 14 is formed on the semiconductor substrate 12 as shown in FIG. 2A.
  • a base is formed on the insulating film 14, and a wiring 16 made of Au is formed on the base by a method such as vapor deposition, sputtering, or plating, as shown in FIG. 2 (b).
  • ions are implanted from a direction perpendicular to the semiconductor substrate 12 by the ion implantation method.
  • the injection conditions are, for example, an acceleration energy of 5 to 50 keV and a dose amount of 1 ⁇ 10 12 ions / cm 2 or more.
  • an ion implantation layer 16a and an ion implantation layer 14a are formed on the upper surface of the wiring 16 and the upper surface of the insulating film 14, respectively.
  • the ion implantation layer 16a formed on the upper surface of the wiring 16 becomes chemically unstable when ions are implanted.
  • the insulating film 18 is formed by a CVD method, an ALD (Atomic Layer Deposition) method, or the like so as to cover the wiring 16.
  • CVD chemical vapor deposition
  • ALD atomic layer Deposition
  • the ion implantation layer 16a on the upper surface of the wiring 16 is chemically unstable, the adhesion between the wiring 16 and the insulating film 18 is improved, and the ion species is the insulating film 14. It is not necessary to form a protective resist on the insulating film 14 before ion implantation because the insulating property is not impaired even if the film is implanted into the insulating film 14.
  • FIG. 3 is a diagram of the semiconductor device 30 according to the second embodiment.
  • the semiconductor device 30 is the same as the semiconductor device 10 according to the first embodiment, except that the ion implantation layer 36a is also formed on the side surface of the wiring 36.
  • FIG. 4 is a diagram showing a manufacturing method of the semiconductor device 30 according to the second embodiment.
  • FIGS. 4A to 4D are sequentially carried out.
  • the method of manufacturing the semiconductor device 30 according to the second embodiment is the same as that of the first embodiment, except that the oblique ion implantation method is used for the ion implantation (FIG. 4 (c)).
  • oblique ion implantation ions are implanted at an angle from a direction perpendicular to the semiconductor substrate 12.
  • the ion implantation layer 36a is also formed on the side surface of the wiring 36.
  • the oblique ion implantation method either a method of implanting while rotating the wafer around the vertical direction or a method of split implantation while changing the rotation angle of the wafer may be used.
  • the ion implantation layer 36a is also formed on the side surface of the wiring 36, so that the adhesion between the wiring 36 and the insulating film 18 is further improved.
  • FIG. 5 is a diagram of the semiconductor device 50 according to the third embodiment.
  • the semiconductor device 50 is the same as the semiconductor device 10 according to the first embodiment, but the distribution of the ions injected into the wiring 56 and the insulating film 54 in the vertical direction is different.
  • FIG. 6 is a diagram showing a manufacturing method of the semiconductor device 50 according to the third embodiment.
  • FIGS. 6A to 6D are sequentially carried out.
  • the ion implantation is performed before the insulating film 58 is formed, but in the third embodiment, the ion implantation is performed after the insulating film 58 is formed (FIGS. 6 (c) and 6 (d)). Ion implantation is performed not only on the wiring 56 and the insulating film 54 but also on the insulating film 58.
  • the ion implantation condition is set so that the peak of the distribution of the ions to be implanted into the wiring 56 in the vertical direction is near the interface between the upper surface of the wiring 56 and the insulating film 58.
  • FIG. 7 is an enlarged view of the vicinity of the upper right of the wiring 56 in FIG. 5, and shows the peak position of the ion distribution.
  • the injection conditions vary depending on the thickness of the insulating film 58, etc., but as an example, when the insulating film is SiN with a thickness of 100 nm and the ion species is Ar, the acceleration energy is 150 keV and the dose amount is 1 ⁇ 10 12 ions / cm 2 or more. is there.
  • the adhesion between the wiring 56 and the insulating film 58 is further improved.
  • the peak of the distribution in the vertical direction exists inside the upper surface of the wiring 16. Therefore, the adhesion between the wiring 56 and the insulating film 58 is higher in the semiconductor device 50 according to the third embodiment than in the first embodiment.
  • the oblique ion implantation method similar to that of the second embodiment may be used for ion implantation. In that case, the adhesion between the wiring 56 and the insulating film 58 is further improved.
  • FIG. 8 is a diagram of the semiconductor device 70 according to the fourth embodiment.
  • the semiconductor device 70 is the same as the semiconductor device 30 according to the second embodiment, except that there is no ion-implanted layer on the upper surface of the insulating film 74 and the ion-implanted ion species are limited.
  • Ion species include Ar, N, etc., which do not impair the insulating property even when implanted in the insulating film 14, and B, Si, Pd, Ti, Ta, Al, Co, etc., when ion-implanted, the electrical conductivity of the insulating film. You may use the one which becomes high. As described later, these ion species are injected into the wiring made of Au and act as impurities on Au.
  • impurity elements the elements that are the source of these ions are referred to as impurity elements here.
  • concentration of impurity elements in the ion-implanted layer 76a is 1 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 21 cm -3 or less.
  • the manufacturing method of the semiconductor device 70 according to the fourth embodiment will be described below.
  • the process of forming the wiring 76 as shown in FIG. 9A is the same as that of the second embodiment.
  • the resist 82 is formed in the region of the upper surface of the insulating film 74 that is not covered by the wiring 76 as shown in FIG. 9B.
  • the resist 82 is thermally deformed by applying a heat treatment at 90 ° C. or higher to expose at least a part of the side surface of the wiring 76 in contact with the resist 82.
  • ions are implanted into the upper surface of the wiring 76, at least a part of the side surface of the wiring 76, and the upper surface of the resist 82 by the oblique ion implantation method.
  • an ion implantation layer 76a is formed on the upper surface of the wiring 76 and at least the upper surface of the side surface of the wiring 76, and the ion implantation layer 82a is formed on the upper surface of the resist 82.
  • the ion implantation layer 76a formed on the upper surface of the wiring 16 is in a chemically unstable state due to the injection of ions, which are impurities.
  • the ion type is B, Si, Pd, Ti, Ta, Al, Co, or the like, the ion implantation layer 76a becomes an alloy with Au if it is annealed after ion implantation.
  • the insulating film 78 is formed so as to cover the wiring 76 as shown in FIG. 10 (c).
  • the resist 82 when the ions are implanted, the resist 82 is placed on the insulating film 74, and the ions are not directly implanted on the insulating film 74, so that the insulating film 74 is not damaged. Further, even if the insulating property is impaired when the ion species is driven into the insulating film 74, the insulating property of the insulating film 74 is not impaired.
  • the ion implantation layer 76a becomes an alloy with Au if annealed after ion implantation, so that the adhesion between the wiring 76 and the insulating film 78 is improved. Further improve.
  • the wiring 116 is formed on the semiconductor substrate 112.

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Abstract

半導体装置（１０）の製造方法は、半導体基板（１２）の上に第１の絶縁膜（１４）を形成する工程と、第１の絶縁膜（１４）の上に少なくとも最上層がＡｕでできた配線（１６）を形成する工程と、配線（１６）の上面および第１の絶縁膜（１４）の上面のうち配線（１６）に覆われていない領域に、絶縁膜（１４）に注入されても絶縁性を損なわないイオンを注入する工程と、配線（１６）を覆う第２の絶縁膜（１８）を形成する工程とをこの順に備える。配線（１６）の上面に、第１の絶縁膜（１４）に注入されても絶縁性を損なわないイオンを注入するため、配線（１６）と第２の絶縁膜（１８）との密着性向上と製造工程数の増加抑制を両立できる。

Description

半導体装置の製造方法および半導体装置
　この発明は、Ａｕでできた配線を絶縁膜で覆った半導体装置の製造方法、および半導体装置に関する。
　ＧａＡｓやＧａＮ等の化合物半導体を用いた高周波デバイスではトランジスタの配線の材料に信頼性に優れるＡｕが用いられている。またデバイスの保護を目的として配線は絶縁膜（例えばＳｉＯやＳｉＮ）で覆われている。しかしながらＡｕは化学的に安定しているため、Ａｕ上に絶縁膜を形成した場合、Ａｕと絶縁膜との密着力が弱く配線上の絶縁膜が剥がれやすい問題がある。
　この問題に対して、Ａｕ上にイオン注入法によりＴｉを注入しアニールすることで配線表層にＡｕ－Ｔｉ合金層を形成し絶縁膜の密着性を向上したものがある（例えば、特許文献１参照）。
　また別の対策として、Ａｕ上にイオン注入法によりＳｉを注入しアニールすることで配線表面にＳｉを含有する領域を設け、同じくＳｉを含有する絶縁膜との密着性を高める方法も示されている（例えば、特許文献２参照）。
特開平０６－０６１２２５号公報 特開平０７－２７３１０７号公報
　しかしＡｕでできた配線にＴｉイオンまたはＳｉイオンを注入する場合、配線の下にある絶縁膜にイオンが注入されると配線下の絶縁膜の絶縁性が損なわれる。そのためイオン注入時に配線下の絶縁膜にイオンが注入されないように配線下の絶縁膜の上にレジストを形成する必要があり、製造工程数が増加するという問題がある。
　この発明は上記の問題を解消するためになされたもので、その目的はＡｕでできた配線と配線上の絶縁膜との密着性向上と製造工程数の増加抑制を両立する半導体装置の製造方法および半導体装置を得ることである。
　この発明に係る半導体装置の製造方法は、半導体基板の上に第１の絶縁膜を形成する工程と、第１の絶縁膜の上に少なくとも最上層がＡｕでできた配線を形成する工程と、配線の上面および第１の絶縁膜の上面のうち配線に覆われていない領域に、絶縁膜に注入されても絶縁性を損なわないイオンを注入する工程と、配線を覆う第２の絶縁膜を形成する工程とをこの順に備える。
　またこの発明に係る半導体装置は、半導体基板と、半導体基板の上の第２の絶縁膜と第１の絶縁膜の上の少なくとも最上層がＡｕでできた配線と、配線を覆う第２の絶縁膜とを備え、配線の上面付近および第１の絶縁膜の上面のうち配線に覆われていない領域付近に、絶縁性非破壊元素が１×１０１７ｃｍ－３以上１×１０２１ｃｍ－３以下の濃度で存在する。
　この発明の半導体装置の製造方法および半導体装置によれば、Ａｕでできた配線の上面に、配線下の絶縁膜に注入されても絶縁性を損なわないイオンを注入するため、Ａｕでできた配線と配線上の絶縁膜との密着性向上と製造工程数の増加抑制を両立できる。
実施の形態１に係る半導体装置の断面図である。 実施の形態１に係る半導体装置の製造方法を示す図である。 実施の形態２に係る半導体装置の断面図である。 実施の形態２に係る半導体装置の製造方法を示す図である。 実施の形態３に係る半導体装置の断面図である。 実施の形態３に係る半導体装置の製造方法を示す図である。 実施の形態３に係る半導体装置の配線上面におけるイオンの分布のピーク位置を示す図である。 実施の形態４に係る半導体装置の断面図である。 実施の形態４に係る半導体装置の製造方法を示す図である。 実施の形態４に係る半導体装置の製造方法を示す図である。 半導体基板と配線の間に絶縁膜がない半導体装置の断面図である。
実施の形態１．
　図１は実施の形態１に係る半導体装置１０の図である。半導体装置１０は半導体基板１２を備える。半導体基板１２はＧａＡｓ、ＧａＮ、ＳｉＣまたはＳｉなどからなる。
　半導体基板１２上に絶縁膜１４が形成されている。絶縁膜１４はポリイミド、ＢＣＢ（ベンゾシクロブテン）またはＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）膜などからなる。ここでＣＶＤ膜とはＣＶＤ法で形成されたＳｉＯ、ＳｉＮなどの絶縁膜である。
　絶縁膜１４上に配線１６が形成されている。配線１６はＴｉ、Ｔａ、Ｃｒ、Ｔｉ／ＰｔまたはＴｉＷなどの下地の上にＡｕで形成されたものである。ここでＴｉ／ＰｔとはＴｉの上にＰｔが形成された構造のことであり、ＴｉＷとはＴｉとＷの合金のことである。配線１６は下地の上にＡｕで形成されたものであるため、配線１６の少なくとも最上層はＡｕでできている。また配線１６の側面のうち下地より上はＡｕでできているため、配線１６の側面の少なくとも上部はＡｕでできている。なお下地はＡｕに比べて薄いため、図では省略した。
　配線１６の上面にイオンが注入されたイオン注入層１６ａが形成されている。イオン種は、絶縁膜１４に注入されても絶縁性を損なわない元素であり、ここでは絶縁性非破壊元素と呼ぶ。絶縁性非破壊元素は具体的にはＡｒまたはＮなどである。また絶縁膜１４の上面のうち配線１６に覆われていない領域にもイオン注入層１４ａが形成されている。イオン注入層１６ａおよびイオン注入層１４ａの絶縁性非破壊元素の濃度は１×１０１７ｃｍ－３以上１×１０２１ｃｍ－３以下である。
　配線１６を覆うように絶縁膜１８が形成されている。絶縁膜１８はＳｉＯ、ＳｉＮ、ＳｉＯＮ、ＡｌＯまたはＴａＯ等である。
　以下に実施の形態１に係る半導体装置１０の製造方法を説明する。まず図２（ａ）のように半導体基板１２の上に絶縁膜１４を形成する。
　次に絶縁膜１４の上に下地を形成し、下地の上に図２（ｂ）のように、Ａｕでできた配線１６を蒸着、スパッタリングまたはメッキ等の方法で形成する。
　次に図２（ｃ）のようにイオン注入法により半導体基板１２に対して垂直な方向からイオンを注入する。注入条件は例えば加速エネルギーが５～５０ｋｅＶ、ドーズ量が１×１０１２ｉｏｎｓ／ｃｍ２以上である。イオン注入により配線１６の上面および絶縁膜１４の上面にそれぞれイオン注入層１６ａとイオン注入層１４ａが形成される。配線１６の上面に形成されたイオン注入層１６ａは、イオンが注入されることで化学的に不安定な状態となる。
　次に図２（ｄ）のように配線１６を覆うように絶縁膜１８をＣＶＤ法またはＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法等で形成する。
　以上のとおり実施の形態１によれば配線１６の上面のイオン注入層１６ａが化学的に不安定であるため、配線１６と絶縁膜１８との密着力が向上し、さらにイオン種は絶縁膜１４に注入されても絶縁性を損なわないものであるため、イオン注入前に絶縁膜１４の上に保護用のレジストを形成する必要がない。
実施の形態２．
　図３は実施の形態２に係る半導体装置３０の図である。半導体装置３０は実施の形態１に係る半導体装置１０と同様だが、配線３６の側面にもイオン注入層３６ａが形成されている点が異なる。
　図４は実施の形態２に係る半導体装置３０の製造方法を示す図である。この製造方法では図４（ａ）から（ｄ）を順に実施する。実施の形態２に係る半導体装置３０の製造方法は実施の形態１と同様だが、イオン注入に斜めイオン注入法を用いる点が異なる（図４（ｃ））。斜めイオン注入では半導体基板１２に対して垂直な方向から傾けてイオンを注入する。これにより配線３６の側面にもイオン注入層３６ａが形成される。斜めイオン注入法としては鉛直方向を軸としてウエハを回転しながら注入する方法と、ウエハの回転角を変えながら分割注入する方法のどちらを用いてもよい。
　以上のとおり実施の形態２によれば配線３６の側面にもイオン注入層３６ａが形成されるため、配線３６と絶縁膜１８との密着性がさらに向上する。
実施の形態３．
　図５は実施の形態３に係る半導体装置５０の図である。半導体装置５０は実施の形態１に係る半導体装置１０と同様だが、配線５６および絶縁膜５４に注入されたイオンの鉛直方向における分布が異なる。
　図６は実施の形態３に係る半導体装置５０の製造方法を示す図である。この製造方法では図６（ａ）から（ｄ）を順に実施する。実施の形態１ではイオン注入を絶縁膜５８形成前に実施するが、実施の形態３では絶縁膜５８を形成したあとイオン注入を実施する（図６（ｃ）と（ｄ））。イオン注入は配線５６と絶縁膜５４だけでなく絶縁膜５８にもなされる。
　イオン注入条件を、配線５６に注入するイオンの鉛直方向における分布のピークが配線５６の上面と絶縁膜５８の界面付近にあるように設定する。図７は図５における配線５６の右上付近を拡大した図で、イオンの分布のピーク位置を示している。注入条件は絶縁膜５８の厚さ等により変わるが、一例として絶縁膜が厚さ１００ｎｍのＳｉＮ、イオン種がＡｒの場合、加速エネルギーが１５０ｋｅＶ、ドーズ量が１×１０１２ｉｏｎｓ／ｃｍ２以上である。
　以上のとおり実施の形態３によれば配線５６に注入されるイオンの鉛直方向における分布のピークが配線５６の上面と絶縁膜５８の界面付近にあるため、配線５６と絶縁膜５８との密着性がさらに向上する。一方実施の形態１のように配線１６の上から直接イオン注入すると鉛直方向の分布のピークは配線１６の上面より内部に存在することになる。そのため実施の形態１に比べて実施の形態３に係る半導体装置５０のほうが配線５６と絶縁膜５８との密着性が高くなる。
　なおイオン注入に実施の形態２と同様の斜めイオン注入法を用いてもかまわない。その場合は配線５６と絶縁膜５８の密着性がさらに向上する。
実施の形態４．
　図８は実施の形態４に係る半導体装置７０の図である。半導体装置７０は実施の形態２に係る半導体装置３０と同様だが、絶縁膜７４の上面にイオン注入層がない点と、イオン注入されたイオン種の限定が異なる。イオン種は、絶縁膜１４に注入されても絶縁性を損なわないＡｒ、Ｎなどに加え、Ｂ、Ｓｉ、Ｐｄ、Ｔｉ、Ｔａ、ＡｌまたはＣｏなど、イオン注入されると絶縁膜の電気伝導度が高くなるものを用いてもよい。これらのイオン種は後述するようにＡｕでできた配線に注入され、Ａｕに対して不純物として働くため、これらのイオンの元となる元素をここでは不純物元素と呼ぶ。イオン注入層７６ａ中の不純物元素の濃度は１×１０１７ｃｍ－３以上１×１０２１ｃｍ－３以下である。
　以下に実施の形態４に係る半導体装置７０の製造方法を説明する。図９（ａ）のように配線７６を形成するまでの工程は実施の形態２と同様である。
　図９（ａ）のあと、図９（ｂ）のように絶縁膜７４の上面のうち配線７６に覆われていない領域にレジスト８２を形成する。
　次に図９（ｃ）のように９０℃以上の熱処理を加えてレジスト８２を熱変形させ、配線７６の側面のうちレジスト８２と接触する領域の少なくとも一部を露出させる。
　次に図１０（ａ）のように斜めイオン注入法により配線７６の上面、配線７６の側面の少なくとも一部、およびレジスト８２の上面にイオンを注入する。イオン注入により配線７６の上面および配線７６の側面の少なくとも上部にイオン注入層７６ａが形成され、レジスト８２の上面にイオン注入層８２ａが形成される。配線１６の上面に形成されたイオン注入層７６ａは、不純物であるイオンが注入されることで化学的に不安定な状態となる。またイオン種がＢ、Ｓｉ、Ｐｄ、Ｔｉ、Ｔａ、ＡｌまたはＣｏなどの場合、イオン注入後にアニールすればイオン注入層７６ａがＡｕとの合金となる。
　次に図１０（ｂ）のようにレジスト８２を除去する。
　次に図１０（ｃ）のように配線７６を覆うように絶縁膜７８を形成する。
　以上のとおり実施の形態４によればイオン注入の際、絶縁膜７４の上にレジスト８２があり、絶縁膜７４の上には直接イオンが注入されないため、絶縁膜７４がダメージを受けない。またイオン種が絶縁膜７４に打ち込まれた場合にその絶縁性を損なうものであっても絶縁膜７４の絶縁性が損なわれない。
　またイオン種がＢ、Ｓｉ、Ｐｄ、Ｔｉ、Ｔａ、ＡｌまたはＣｏなどの場合、イオン注入後にアニールすればイオン注入層７６ａがＡｕとの合金となるため、配線７６と絶縁膜７８の密着性がさらに向上する。
　なお全ての実施の形態で半導体基板と配線の間に絶縁膜があるとしたが、なくてもよい。その場合、例えば図１１のように配線１１６が半導体基板１１２の上に形成される。
１０，３０，５０，７０，１１０　半導体装置
１２，１１２　半導体基板
１４，５４，７４　絶縁膜
１４ａ，１４ａ，５４ａ，８２ａ，１１２ａ　イオン注入層
１６，３６，５６，７６，１１６　配線
１６ａ，３６ａ，５６ａ，７６ａ，１１６ａ　イオン注入層
１８，１８，５８，７８，１１８　絶縁膜
８２　レジスト

Claims (12)

  1. 　半導体基板の上に第１の絶縁膜を形成する工程と、
    　前記第１の絶縁膜の上に少なくとも最上層がＡｕでできた配線を形成する工程と、
    　前記配線の上面および前記第１の絶縁膜の上面のうち前記配線に覆われていない領域に、前記絶縁膜に注入されても絶縁性を損なわないイオンを注入する工程と、
    　前記配線を覆う第２の絶縁膜を形成する工程とをこの順に備える半導体装置の製造方法。
  2. 　半導体基板の上に第１の絶縁膜を形成する工程と、
    　前記第１の絶縁膜の上に少なくとも最上層がＡｕでできた配線を形成する工程と、
    　前記配線を覆う第２の絶縁膜を形成する工程と、
    　前記配線の上面および前記第１の絶縁膜の上面のうち前記配線に覆われていない領域に、前記絶縁膜に注入されても絶縁性を損なわないイオンを注入する工程と、
    　前記配線および前記第２の絶縁膜に注入された前記イオンの分布のピークがそれぞれ、前記配線の上面と前記第２の絶縁膜の界面付近にある半導体装置の製造方法。
  3. 　前記イオンはＡｒまたはＮである請求項１または２に記載の半導体装置の製造方法。
  4. 　前記配線の側面の少なくとも上部がＡｕでできており、
    　前記イオンを注入する方法として斜めイオン注入法を用い、前記配線の側面にも前記イオンを注入する請求項１～３のいずれか１項に記載の半導体装置の製造方法。
  5. 　半導体基板の上に第１の絶縁膜を形成する工程と、
    　前記第１の絶縁膜の上に少なくとも最上層および側面の少なくとも上部がＡｕでできた配線を形成する工程と、
    　前記第１の絶縁膜の上面のうち前記配線に覆われていない領域にレジストを形成する工程と、
    　前記レジストを熱処理で変形させ、前記配線の側面のうち前記レジストと接触する領域の少なくとも一部を露出させる工程と、
    　前記配線の上面、前記配線の側面の少なくとも上部および前記レジストの上面に斜めイオン注入法を用いてイオンを注入する工程と、
    　前記レジストを除去する工程と、
    　前記配線を覆う第２の絶縁膜を形成する工程とをこの順に備える半導体装置の製造方法。
  6. 　前記イオンはＢ、Ｓｉ、Ｐｄ、Ｔｉ、Ｔａ、Ａｌ、Ｃｏ、ＡｒまたはＮのいずれか１つである請求項５に記載の半導体装置の製造方法。
  7. 　半導体基板と、
    　前記半導体基板の上の第１の絶縁膜と
    　前記第１の絶縁膜の上の少なくとも最上層がＡｕでできた配線と、
    　前記配線を覆う第２の絶縁膜とを備え、
    　前記配線の上面付近および前記第１の絶縁膜の上面のうち前記配線に覆われていない領域付近に、絶縁性非破壊元素が１×１０１７ｃｍ－３以上１×１０２１ｃｍ－３以下の濃度で存在する半導体装置。
  8. 　前記絶縁性非破壊元素が前記第２の絶縁膜の下面付近にも存在し、
    　前記配線の上面および前記配線の上面と接する前記第２の絶縁膜の下面における前記絶縁性非破壊元素の分布のピークがそれぞれ、前記配線の上面と前記第２の絶縁膜の界面付近にある請求項７に記載の半導体装置。
  9. 　前記絶縁性非破壊元素はＡｒまたはＮである請求項７または８に記載の半導体装置。
  10. 　前記配線の側面の少なくとも上部がＡｕでできており、
    　前記絶縁性非破壊元素が前記配線の側面付近にも１×１０１７ｃｍ－３以上１×１０２１ｃｍ－３以下の濃度で存在する請求項７～９のいずれか１項に記載の半導体装置。
  11. 　半導体基板と、
    　前記半導体基板の上の第１の絶縁膜と
    　前記第１の絶縁膜の上の少なくとも最上層および側面の少なくとも上部がＡｕでできた配線と、
    　前記配線を覆う第２の絶縁膜とを備え、
    　前記配線の上面付近および側面付近に不純物元素が１×１０１７ｃｍ－３以上１×１０２１ｃｍ－３以下の濃度で存在する半導体装置。
  12. 　前記不純物元素はＢ、Ｓｉ、Ｐｄ、Ｔｉ、Ｔａ、Ａｌ、Ｃｏ、ＡｒまたはＮのいずれか１つである請求項１１に記載の半導体装置。
PCT/JP2019/012435 2019-03-25 2019-03-25 半導体装置の製造方法および半導体装置 WO2020194432A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05109721A (ja) * 1991-10-15 1993-04-30 Nec Corp 半導体集積回路
JPH05275547A (ja) * 1992-03-30 1993-10-22 Nec Corp 半導体装置
JPH0684905A (ja) * 1992-05-27 1994-03-25 Nec Corp 半導体集積回路装置の製造方法
JPH07273107A (ja) * 1994-04-01 1995-10-20 Fujitsu Ltd 半導体装置とその製造方法
JPH08321613A (ja) * 1995-05-26 1996-12-03 Ricoh Co Ltd 半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315332A (ja) * 1992-04-02 1993-11-26 Nec Corp 半導体装置およびその製造方法
JPH0661225A (ja) 1992-04-27 1994-03-04 Nec Corp 半導体装置の製造方法
JPH09293720A (ja) * 1996-04-26 1997-11-11 Sony Corp 半導体装置およびその製造方法
TW517391B (en) * 2001-03-08 2003-01-11 Sanyo Electric Co Method for manufacturing semiconductor device
US6917110B2 (en) * 2001-12-07 2005-07-12 Sanyo Electric Co., Ltd. Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer
US8084352B2 (en) 2007-06-04 2011-12-27 Panasonic Corporation Method of manufacturing semiconductor device
JP2009218381A (ja) * 2008-03-11 2009-09-24 Denso Corp ＳＯＩ（Ｓｉｌｉｃｏｎｏｎｉｎｓｕｌａｔｏｒ）基板の製造方法
JP5482441B2 (ja) * 2010-05-20 2014-05-07 富士ゼロックス株式会社 化合物半導体素子の製造方法
JP6061225B2 (ja) 2013-08-23 2017-01-18 マスセット株式会社 テーブル用脚キャップ
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
JP6801840B2 (ja) 2016-09-27 2020-12-16 住友電工デバイス・イノベーション株式会社 半導体装置
US10186454B2 (en) * 2017-06-15 2019-01-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure having etch stop layer and method of forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05109721A (ja) * 1991-10-15 1993-04-30 Nec Corp 半導体集積回路
JPH05275547A (ja) * 1992-03-30 1993-10-22 Nec Corp 半導体装置
JPH0684905A (ja) * 1992-05-27 1994-03-25 Nec Corp 半導体集積回路装置の製造方法
JPH07273107A (ja) * 1994-04-01 1995-10-20 Fujitsu Ltd 半導体装置とその製造方法
JPH08321613A (ja) * 1995-05-26 1996-12-03 Ricoh Co Ltd 半導体装置の製造方法

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