JPWO2018155162A1 - シールド板付き電子部品及び電子部品用シールド板 - Google Patents
シールド板付き電子部品及び電子部品用シールド板 Download PDFInfo
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- JPWO2018155162A1 JPWO2018155162A1 JP2019501193A JP2019501193A JPWO2018155162A1 JP WO2018155162 A1 JPWO2018155162 A1 JP WO2018155162A1 JP 2019501193 A JP2019501193 A JP 2019501193A JP 2019501193 A JP2019501193 A JP 2019501193A JP WO2018155162 A1 JPWO2018155162 A1 JP WO2018155162A1
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- Prior art keywords
- electronic component
- shield plate
- main surface
- metal film
- shield
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- 239000002184 metal Substances 0.000 claims abstract description 277
- 229910052751 metal Inorganic materials 0.000 claims abstract description 277
- 239000000919 ceramic Substances 0.000 claims abstract description 198
- 239000010408 film Substances 0.000 claims description 198
- 239000004020 conductor Substances 0.000 claims description 134
- 239000011347 resin Substances 0.000 claims description 96
- 229920005989 resin Polymers 0.000 claims description 96
- 238000007789 sealing Methods 0.000 claims description 91
- 230000004907 flux Effects 0.000 claims description 20
- 239000010409 thin film Substances 0.000 claims description 13
- 238000004804 winding Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 64
- 239000012790 adhesive layer Substances 0.000 description 42
- 239000000758 substrate Substances 0.000 description 35
- 230000000694 effects Effects 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 239000002131 composite material Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 6
- 230000000644 propagated effect Effects 0.000 description 5
- 239000012762 magnetic filler Substances 0.000 description 4
- 230000035699 permeability Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910000889 permalloy Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/04—Punching, slitting or perforating
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B9/00—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
- B32B9/005—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising one layer of ceramic material, e.g. porcelain, ceramic tile
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B9/00—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
- B32B9/04—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising such particular substance as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B9/045—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising such particular substance as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H05K1/02—Details
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- H05K1/02—Details
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- H05K9/0007—Casings
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- H05K9/0073—Shielding materials
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/04—Punching, slitting or perforating
- B32B2038/045—Slitting
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
- B32B2307/212—Electromagnetic interference shielding
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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Abstract
Description
本発明の第1の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図1(A)は、本発明の第1の実施形態に係る電子部品用シールド板の第1主面側からの外観斜視図である。図1(B)は、本発明の第1の実施形態に係る電子部品用シールド板の第2主面側からの外観斜視図である。図2(A)は、本発明の第1の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。図2(B)は、図2(A)におけるシールド板の一部分を拡大した図である。図1(A)、図1(B)では、図を見やすくするために、一部の符号の付記を省略している。
本発明の第2の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図3は本発明の第2の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第3の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図4は本発明の第3の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第4の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図5(A)は、本発明の第4の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。図5(B)は、図5(A)におけるシールド板の一部分を拡大した図である。図5(A)では、図を見やすくするために、一部の符号の付記を省略している。
本発明の第5の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図6(A)は、本発明の第5の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。図6(B)は、図6(A)におけるシールド板の一部分を拡大した図である。
本発明の第6の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図7は本発明の第6の実施形態に係るシールド板付き電子部品1Eの構成を示す部分分解斜視図である。図8(A)は、本発明の第6の実施形態に係る図7のA−A断面を示す図である。図8(B)は、図8(A)の部分拡大図である。
本発明の第7の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図9は本発明の第7の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第8の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図10は本発明の第8の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第9の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図11は本発明の第9の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第10の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図12は本発明の第10の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第11の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図13は本発明の第11の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第12の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図14は、本発明の第12の実施形態に係る電子部品用シールド板における、第2主面側からの外観斜視図である。
本発明の第13の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図15は、本発明の第13の実施形態に係る電子部品用シールド板における、第2主面102側からの外観斜視図である。
本発明の第14の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図16は本発明の第14の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第15の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図17は本発明の第15の実施形態に係るシールド板付き電子部品の構成を示す側面断面図である。
本発明の第16の実施形態に係るシールド板付き電子部品について、図を参照して説明する。図18(A)、は本発明の第16の実施形態に係るシールド板付き電子部品を第1主面側からの正面概要図である。図18(B)は、コイルが配置されたLTCC基板21の一部分を拡大した斜視図である。図19は、本発明の第16の実施形態に係るシールド板付き電子部品の構成を示す側面の概要を示す図である。
d20、d41、d42、d43…厚み
d3、d4…合計幅
1、1A、1B、1C、1D、1E、1F、1G、1H、1J、1K、1M、1N、1P、1Q、1R…シールド板付き電子部品
10、10A、10B、10C、10D、10E、10F、10G、10H、10J、10K、10M、10N、10P、10Q、10R…電子部品用シールド板
11、11A、11B、11C、11D、11E、11F、11G、11H、11N、11P、11Q、11R、13B、13C、13D、17H…金属膜
12、12A、12B、12C、12D、12E、12F、12G、12H、12N、12P、12Q、12R…磁性体セラミック焼結板
14D、14H…半田
15、15A、15C、15D、15E、15F、15G、15H、15N、15P、15Q、15R…接着層
16C、16E…ビア導体
20、20A、20B、20C、20D、70、90…プリント配線基板
21…LTCC基板
31、32、36、61A、61C…接続導体
33、34…グランド用端子導体
35…外部接続用端子導体
40、40J、40K…封止樹脂
41、42、43、44…部品実装用ランド導体
51、52、53、54…表面実装電子部品
62A、62C、62D、64A、64B、64C、64D…ビアホール導体
62B…金属ポスト
63A、63B、63C、63D…端子導体
70…プリント配線基板
71…金属枠体
81、82…空隙
101、101A、101B、101C、101D、101E、101F、101G、101N、101P、101Q、201、201A、201B、201C、201D、701…第1主面
102、102A、102B、102C、102D、102E、102G、102H、102N、102P、102R、202、202A、202B、202C、202D、702…第2主面
110、111…部品位置
500、600…インダクタ導体
550…第1磁束
650…第2磁束
810、820…開口
Claims (16)
- 配線基板と、
前記配線基板の表面に実装された表面実装部品と、
前記表面実装部品の天面側に取り付けられたシールド板と、
を備え、
前記シールド板は、
第1主面及び第2主面を有する磁性体セラミック焼結板と、
前記磁性体セラミック焼結板の前記第1主面に設けられた第1金属膜と、
を有する、シールド板付き電子部品。 - 前記磁性体セラミック焼結板の前記第2主面には、複数の切れ目が形成されている、
請求項1に記載のシールド板付き電子部品。 - 前記第1金属膜は金属薄膜である、
請求項1乃至請求項2に記載のシールド板付き電子部品。 - 前記第1主面に第1金属膜を有し、
前記第2主面に第2金属膜を有する、
請求項3に記載のシールド板付き電子部品。 - 前記第2金属膜は金属薄膜である、
請求項4に記載のシールド板付き電子部品。 - 前記磁性体セラミック焼結板の前記第1主面が、
前記表面実装部品に対向している、
請求項1乃至請求項5に記載のシールド板付き電子部品。 - 前記配線基板の表面電極と前記第1金属膜とを接続する導体を有する、
請求項6に記載のシールド板付き電子部品。 - 前記配線基板の表面に設けられた封止樹脂を有し、前記シールド板は前記封止樹脂の天面側に取り付けられる、
請求項1乃至請求項7に記載のシールド板付き電子部品。 - 前記磁性体セラミック焼結板を貫通し、
一方端が前記第1主面に露出し、他方端が前記第2主面に露出する、
ビア電極を備える、
請求項1乃至請求項8に記載のシールド板付き電子部品。 - 配線基板と、
前記配線基板の表面に実装された表面実装部品と、
前記表面実装部品の天面側に取り付けられたシールド板と、
を備え、
前記シールド板の一方主面に、複数の切れ目が形成されており、
前記一方主面のみに、金属膜が設けられている、
シールド板付き電子部品。 - 第1主面及び第2主面を有する磁性体セラミック焼結板と、
前記磁性体セラミック焼結板の前記第1主面及び前記第2主面の少なくとも一方に設けられた金属膜と、を備える、
電子部品用シールド板。 - 前記表面実装部品は、
前記配線基板に、隣り合うように実装された、第1表面実装部品と、第2表面実装部品を含み、
前記第1表面実装部品と、前記第2表面実装部品と、を覆う封止樹脂と、を備え、
前記封止樹脂は、空隙を備え、
前記空隙は、前記第1表面実装部品と、前記第2表面実装部品が配置された領域の厚みよりも薄い薄厚部を構成する、請求項1に記載のシールド板付き電子部品。 - 前記空隙は、前記封止樹脂の天面または下面に開口する、請求項12に記載のシールド付き電子部品。
- 前記薄厚部は、
前記第1金属膜の一方主面から前記配線基板の一方主面を平面視して、前記第1表面実装部品と、前記第2表面実装部品と、の間に形成されていることを特徴とする、請求項12または請求項13に記載のシールド板付き電子部品。 - 前記表面実装部品は、
前記配線基板に、隣り合うように実装された、第1表面実装部品と、第2表面実装部品を含み、
前記第1金属膜の一方主面から前記配線基板の一方主面を平面視して、前記第1表面実装部品と、前記第2表面実装部品と、の間に複数の切れ目が形成され、
前記切れ目は、前記第1表面実装部品と前記第2表面実装部品が配置された領域の厚みよりも薄い薄厚部を構成する、請求項1に記載のシールド板付き電子部品。 - 前記第1表面実装部品の天面側にインダクタ導体を備え、
前記表面実装部品は、第1磁束を発生し、
前記天面側のインダクタ導体は第2磁束を発生し、
前記天面側のインダクタ導体は、
前記第1金属膜の一方主面から前記配線基板の一方主面を平面視して、少なくとも開口の一部が前記第1表面実装部品と重なる位置に、前記第1表面実装部品に対向するよう配置され、
前記天面側のインダクタ導体の巻回方向は、前記天面側のインダクタ導体から発生する第2磁束と前記第1表面実装部品から発生する第1磁束とが互いに弱め合う方向に設定される、請求項12乃至請求項14のいずれかに記載のシールド板付き電子部品。
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