JPWO2017086069A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2017086069A1 JPWO2017086069A1 JP2017551778A JP2017551778A JPWO2017086069A1 JP WO2017086069 A1 JPWO2017086069 A1 JP WO2017086069A1 JP 2017551778 A JP2017551778 A JP 2017551778A JP 2017551778 A JP2017551778 A JP 2017551778A JP WO2017086069 A1 JPWO2017086069 A1 JP WO2017086069A1
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Abstract
Description
実施の形態1にかかる半導体装置として、高耐圧集積回路装置(HVIC)の構成について説明する。図1は、実施の形態1にかかる半導体装置の平面レイアウトを示す平面図である。例えば、電力変換用ブリッジ回路の一相分(不図示)を構成する直列接続された2つのIGBT(Insulated Gate Bipolar Transistor:絶縁ゲート型バイポーラトランジスタ)のうちの高電位側(ハイサイド側)のIGBT(以下、上アームのIGBTとする)を駆動するHVICを例に説明する。図1に示す実施の形態1にかかる半導体装置は、同一の半導体基板(半導体チップ)100上に高電位側領域101および低電位側領域102を備え、これらの領域をHVJT103で電気的に分離したHVICである。
次に、実施の形態2にかかる半導体装置の構成について説明する。図5Aは、実施の形態2にかかる半導体装置の平面レイアウトを示す平面図である。図5Bは、図5Aの要部を拡大して示す平面図である。図5Bには、図5AのnchMOS領域86aを拡大して示す。図5Aの切断線A−A’、切断線B−B’および切断線C−C’における断面構造は、実施の形態1(それぞれ図2〜4参照)と同様である。
次に、実施の形態3にかかる半導体装置の構造について説明する。図6は、実施の形態3にかかる半導体装置の平面レイアウトを示す平面図である。図6の切断線A−A’、切断線B−B’および切断線C−C’における断面構造は、実施の形態1(それぞれ図2,〜4参照)と同様である。
次に、実施の形態4にかかる半導体装置の構造について説明する。図7Aは、実施の形態4にかかる半導体装置の平面レイアウトを示す平面図である。図7Bは、図7Aの要部を拡大して示す平面図である。図7Bには、図7AのnchMOS領域86aを拡大して示す。図7Aの切断線A−A’、切断線B−B’および切断線C−C’における断面構造は、実施の形態1(それぞれ図2〜4参照)と同様である。
次に、実施の形態5にかかる半導体装置の構造について説明する。図8は、実施の形態5にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態5にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、第2HVJT部7において、n-型拡散領域1bとn-型拡散領域3との境界からの距離を、第1p-型分離領域4とハイサイド電源電位H−VDDのn+型領域88とでほぼ同じにしている点である。実施の形態1と同様に、nchMOSFET104の高濃度領域間距離L1をHVJT103の寄生ダイオード105の高濃度領域間距離L2よりも長くしている。図8の切断線A−A’、切断線B−B’および切断線C−C’における断面構造は、実施の形態1(それぞれ図2〜4参照)と同様である。
次に、実施の形態6にかかる半導体装置の構造について説明する。図9は、実施の形態6にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態6にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、レベルアップ用レベルシフト回路のnchMOSFET104を、HVJT103から高電位側領域101にわたって配置している点である。
次に、実施の形態7にかかる半導体装置の構造について説明する。図10は、実施の形態7にかかる半導体装置の構造を示す断面図である。実施の形態7は、実施の形態1の変形例である。図10には、図1の切断線C−C’における断面構造、すなわち第1HVJT部6のダイオード領域6bの断面構造を示す。実施の形態7にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、n型拡散領域1aとn-型拡散領域3とを電気的に分離するp-型分離領域114を拡散領域としている点である。p-型分離領域114は、n-型拡散領域1b(またはn-型拡散領域3)を深さ方向に貫通して基板裏面側のp型領域10に達していればよく、例えば第2p-型分離領域5と同一のイオン注入工程で形成されてもよい。
次に、実施の形態8にかかる半導体装置の構造について説明する。図11は、実施の形態8にかかる半導体装置の構造を示す断面図である。実施の形態8は、実施の形態1の変形例である。図11には、図1の切断線C−C’における断面構造、すなわち第1HVJT部6のダイオード領域6bの断面構造を示す。実施の形態8にかかる半導体装置が実施の形態7にかかる半導体装置と異なる点は、次の2点である。1つ目の相違点は、p型支持基板120の上にn-型エピタキシャル層からなるn-型エピ層123を設けて半導体基板100を構成している点である。2つ目の相違点は、ハイサイド回路部を配置するn型拡散領域1aを、n+型埋め込み層121とn型拡散領域122との2層構造とした点である。
次に、実施の形態9にかかる半導体装置の構造について説明する。図12は、実施の形態9にかかる半導体装置の構造を示す断面図である。実施の形態9は、実施の形態1の変形例である。図12には、図1の切断線C−C’における断面構造、すなわち第1HVJT部6のダイオード領域6bの断面構造を示す。実施の形態9にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、基板裏面側のp型領域10から基板おもて面に露出するようにスリット状に残るp型の半導体基板100の一部に、拡散領域からなるp-型分離領域114を形成している点である。p-型分離領域114は、例えば第2p-型分離領域5と同一のイオン注入工程で形成されてもよい。
次に、実施の形態10にかかる半導体装置の構造について説明する。図13は、実施の形態10にかかる半導体装置の平面レイアウトを示す平面図である。図14は、図13の切断線D−D’における断面構造を示す断面図である。図15は、図13の切断線E−E’における断面構造を示す断面図である。図16は、図13の切断線F−F’における断面構造を示す断面図である。図17は、図13の切断線G−G’における断面構造を示す断面図である。具体的には、図14,16にはHVJT103の寄生ダイオード105の断面構造を示し、図15にはnchMOSFET104の断面構造を示す。図17には、第2HVJT部7のpchMOSFET106の断面構造を示す。
次に、実施の形態11にかかる半導体装置として、実施の形態1〜10にかかる半導体装置を適用する回路構成例について説明する。図19は、実施の形態11にかかる半導体装置の回路構成を示す回路図である。例えば、電力変換用ブリッジ回路150に接続され、電力変換用ブリッジ回路150の一相分を構成する直列接続された第1,2IGBT151,152のハイサイド側の第1IGBT151を駆動するHVIC130を例に説明する。図19に示すHVIC130は、同一の半導体チップ(p型の半導体基板100)上に、ハイサイドゲート駆動回路131、異常検知回路132、入力・制御回路133、レベルアップ用レベルシフト回路134、レベルダウン用レベルシフト回路139、およびHVJT103を備える。直列接続された2つのIGBT151,152は、高電圧電源間に接続される。高電圧電源の電源電圧は、100V以上である。
1b n-型拡散領域
2 n型拡散領域
3 n-型拡散領域(耐圧領域)
4,5,94,114,124 p-型分離領域
4a p-型分離領域の凹状部
5a p-型分離領域の内側部分
5c p-型分離領域の段差部分
6 第1HVJT部
6a,86a,96a nchMOS領域
6b,96b ダイオード領域
6c nchMOS領域の内側に突出した端部
6d,86d nchMOS領域とダイオード領域との境界
7 第2HVJT部
8,88 n+型領域
9a LOCOS膜
9b 層間絶縁膜
10 p型領域
11 p+型コンタクト領域
12 GND電極
13 n型オフセット領域
14 H−VDD電極
20,50 横型nチャネルMOSFET
21,51 p型ウェル領域
22,42,52 n+型ソース領域
23,53 p+型コンタクト領域
24,43,54 n+型ドレイン領域
25,34,44,55,64,74 ゲート絶縁膜
26,35,45,56,65,75 ゲート電極
27,36,66,76 ソース電極
28,46,57,77 ドレイン電極
30,60 横型pチャネルMOSFET
31,61,72 p+型ソース領域
32,62 n+型コンタクト領域
33,63,73 p+型ドレイン領域
41 n型オフセット領域
71 p型オフセット領域
86c nchMOS領域の外側に突出した端部
91,93 n型拡散領域とn-型拡散領域との連続した部分の一部分
100 半導体基板
101 高電位側領域
102 低電位側領域
103 HVJT
104 レベルアップ用レベルシフト回路のnchMOSFET
105 HVJTの寄生ダイオード
106 レベルダウン用レベルシフト回路のpchMOSFET
120 p型支持基板
121 n+型埋め込み層
122 n型拡散領域
123 n-型エピ領域
GND 接地電位
H−VDD ハイサイド電源電位
L−VDD ローサイド電源電位
L1 レベルアップ用レベルシフト回路のnchMOSFETの高濃度領域間距離
L2 HVJTの寄生ダイオードの高濃度領域間距離
L3 レベルダウン用レベルシフト回路のpchMOSFETの高濃度領域間距離
VS 電力変換用ブリッジ回路の上アームのIGBTのエミッタ電位
X n-型拡散領域(耐圧領域)の延在する方向に沿った方向(周方向)
Y 周方向と直交する方向(径方向)
l1 nchMOS領域の周方向の長さ
l2 レベルアップ用レベルシフト回路のnchMOSFETのn+型ドレイン領域の周方向の長さ
l3 レベルアップ用レベルシフト回路のnchMOSFETのn+型ソース領域の周方向の長さ
l4 レベルアップ用レベルシフト回路のnchMOSFETのゲート電極の周方向の長さ
l11 nchMOS領域の内側部分の周方向の長さ(幅)
l21 nchMOS領域の外側部分の周方向の長さ(幅)
l31 p-型分離領域の、nchMOS領域における凹状部の径方向の張り出し幅
l32 p-型分離領域の、ダイオード領域における凹状部の径方向の張り出し幅
w1 n-型拡散領域(耐圧領域)のnchMOS領域における幅
w2 n-型拡散領域(耐圧領域)の第2HVJT部における幅
w3 n-型拡散領域(耐圧領域)のダイオード領域における幅
Claims (12)
- 第1導電型の半導体基板に選択的に設けられた第2導電型の第1半導体領域と、
前記第1半導体領域の周囲を囲む第2導電型の第2半導体領域と、
前記第2半導体領域の周囲を囲む第1導電型の第3半導体領域と、
前記第3半導体領域の内部に選択的に設けられた第2導電型の第4半導体領域と、
前記第1半導体領域もしくは前記第2半導体領域の内部に選択的に設けられた、前記第2半導体領域よりも不純物濃度の高い第2導電型の第5半導体領域と、
前記第3半導体領域の、前記第4半導体領域と前記第2半導体領域とに挟まれた部分の表面上に第1ゲート絶縁膜を介して設けられた第1ゲート電極と、
前記第3半導体領域および前記第4半導体領域に接する第1電極と、
前記第5半導体領域に接する第2電極と、
前記第1半導体領域もしくは前記第2半導体領域の内部に、前記第5半導体領域と離して選択的に設けられた、前記第2半導体領域よりも不純物濃度の高い第2導電型の第6半導体領域と、
前記第3半導体領域の内部に選択的に設けられた、前記第3半導体領域よりも不純物濃度の高い第1導電型の第7半導体領域と、
前記第7半導体領域に接する前記第1電極と、
前記第6半導体領域に接する第3電極と、
を備え、
前記第4半導体領域と前記第5半導体領域との距離は、前記第7半導体領域と前記第6半導体領域との距離よりも長いことを特徴とする半導体装置。 - 少なくとも前記第5半導体領域の内側に設けられた、第1導電型の第8半導体領域をさらに備え、
前記第2半導体領域は、一部を内側または外側に突出させた平面レイアウト、もしくは一部を内側および外側の両方に突出させた平面レイアウトに配置され、
前記第5半導体領域は、前記第2半導体領域の前記一部の内側寄りの部分に配置され、
前記第4半導体領域は、前記第5半導体領域の外側に対向する位置に配置されていることを特徴とする請求項1に記載の半導体装置。 - 前記第2半導体領域は、前記一部を内側に突出させた平面レイアウトに配置され、
前記第5半導体領域は、前記第2半導体領域の前記一部の内側に突出した端部に配置されていることを特徴とする請求項2に記載の半導体装置。 - 前記第2半導体領域の前記一部の内側に突出した端部の幅は、外側に向かうにしたがって広くなっていることを特徴とする請求項3に記載の半導体装置。
- 前記第2半導体領域は、前記一部を外側に突出させた平面レイアウトに配置され、
前記第4半導体領域は、前記第2半導体領域の前記一部の外側に突出した端部における前記第3半導体領域に配置されていることを特徴とする請求項2に記載の半導体装置。 - 前記第2半導体領域の前記一部の外側に突出した端部の幅は、外側に向かうにしたがって狭くなっていることを特徴とする請求項5に記載の半導体装置。
- 前記第2半導体領域は、前記一部以外の部分で前記第1半導体領域に接することを特徴とする請求項2に記載の半導体装置。
- 前記第2半導体領域の内部に選択的に設けられた第1導電型の第9半導体領域と、
前記第1半導体領域もしくは前記第2半導体領域の内部に、前記第9半導体領域と離して、かつ前記第9半導体領域よりも内側に選択的に設けられた第1導電型の第10半導体領域と、
前記第9半導体領域の内部の外側寄りの部分に選択的に設けられた、前記第9半導体領域よりも不純物濃度の高い第1導電型の第11半導体領域と、
前記第2半導体領域の、前記第9半導体領域と前記第10半導体領域とに挟まれた部分の表面上に第2ゲート絶縁膜を介して設けられた第2ゲート電極と、
前記第10半導体領域に接する第4電極と、
前記第11半導体領域に接する第5電極と、
をさらに備え、
前記第11半導体領域は、前記第10半導体領域の外側に対向する位置に配置され、
前記第10半導体領域と前記第11半導体領域との距離は、前記第7半導体領域と前記第6半導体領域との距離よりも長いことを特徴とする請求項2に記載の半導体装置。 - 前記第2半導体領域は、前記第1半導体領域に接する部分を内側または外側に突出させた平面レイアウト、もしくは前記第1半導体領域に接する部分を内側および外側の両方に突出させた平面レイアウトに配置されることを特徴とする請求項8に記載の半導体装置。
- 第1導電型の半導体基板に選択的に設けられた第2導電型の第1半導体領域と、
前記第1半導体領域の周囲を囲み、一部で前記第1半導体領域に接する第2導電型の第2半導体領域と、
前記第2半導体領域の周囲を囲む第1導電型の第3半導体領域と、
前記第1半導体領域もしくは前記第2半導体領域の内部に選択的に設けられた、前記第2半導体領域よりも不純物濃度の高い第2導電型の第6半導体領域と、
前記第3半導体領域の内部に選択的に設けられた、前記第3半導体領域よりも不純物濃度の高い第1導電型の第7半導体領域と、
前記第7半導体領域に接する第1電極と、
前記第6半導体領域に接する第3電極と、
前記第2半導体領域の内部に、前記第6半導体領域と離して選択的に設けられた第1導電型の第9半導体領域と、
前記第2半導体領域の内部に、前記第9半導体領域と離して、かつ前記第9半導体領域よりも内側に選択的に設けられた第1導電型の第10半導体領域と、
前記第9半導体領域の内部の外側寄りの部分に選択的に設けられた、前記第9半導体領域よりも不純物濃度の高い第1導電型の第11半導体領域と、
前記第2半導体領域の、前記第9半導体領域と前記第10半導体領域とに挟まれた部分の表面上に第2ゲート絶縁膜を介して設けられた第2ゲート電極と、
前記第10半導体領域に接する第4電極と、
前記第11半導体領域に接する第5電極と、
を備え、
前記第11半導体領域は、前記第10半導体領域の外側に対向する位置に配置され、
前記第10半導体領域と前記第11半導体領域との距離は、前記第7半導体領域と前記第6半導体領域との距離よりも長いことを特徴とする半導体装置。 - 前記第2半導体領域は、前記第1半導体領域に接する部分を内側または外側に突出させた平面レイアウト、もしくは前記第1半導体領域に接する部分を内側および外側の両方に突出させた平面レイアウトに配置されることを特徴とする請求項10に記載の半導体装置。
- 前記第3半導体領域の外側に第2導電型の第12半導体領域をさらに備えることを特徴とする請求項1〜11のいずれか一つに記載の半導体装置。
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2012227300A (ja) * | 2011-04-19 | 2012-11-15 | Fuji Electric Co Ltd | 半導体装置 |
WO2014041921A1 (ja) * | 2012-09-13 | 2014-03-20 | 富士電機株式会社 | 半導体集積回路装置 |
JP2015170733A (ja) * | 2014-03-07 | 2015-09-28 | 富士電機株式会社 | 半導体装置 |
JP2015173255A (ja) * | 2014-02-19 | 2015-10-01 | 富士電機株式会社 | 高耐圧集積回路装置 |
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JP4917709B2 (ja) * | 2000-03-06 | 2012-04-18 | ローム株式会社 | 半導体装置 |
JP4326835B2 (ja) * | 2003-05-20 | 2009-09-09 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法及び半導体装置の製造プロセス評価方法 |
JP4654574B2 (ja) | 2003-10-20 | 2011-03-23 | トヨタ自動車株式会社 | 半導体装置 |
US8519402B2 (en) * | 2008-07-31 | 2013-08-27 | International Business Machines Corporation | Structure, structure and method of latch-up immunity for high and low voltage integrated circuits |
JP4797203B2 (ja) * | 2008-12-17 | 2011-10-19 | 三菱電機株式会社 | 半導体装置 |
JP5995435B2 (ja) * | 2011-08-02 | 2016-09-21 | ローム株式会社 | 半導体装置およびその製造方法 |
JP5720792B2 (ja) * | 2011-09-16 | 2015-05-20 | 富士電機株式会社 | 高耐圧半導体装置 |
JP5733416B2 (ja) * | 2011-11-14 | 2015-06-10 | 富士電機株式会社 | 高耐圧半導体装置 |
CN104205335B (zh) | 2012-05-28 | 2017-05-17 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
US9761668B2 (en) | 2015-05-08 | 2017-09-12 | Rohm Co., Ltd. | Semiconductor device |
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Publication number | Priority date | Publication date | Assignee | Title |
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