JPWO2013073671A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JPWO2013073671A1 JPWO2013073671A1 JP2013544342A JP2013544342A JPWO2013073671A1 JP WO2013073671 A1 JPWO2013073671 A1 JP WO2013073671A1 JP 2013544342 A JP2013544342 A JP 2013544342A JP 2013544342 A JP2013544342 A JP 2013544342A JP WO2013073671 A1 JPWO2013073671 A1 JP WO2013073671A1
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- insulating film
- semiconductor layer
- unevenness
- interface
- gate insulating
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Abstract
この課題は、ゲート絶縁膜の両界面の凹凸の大きさを特定化することで解決される。
Description
前記半導体層と界面で形成して接触する絶縁膜と、
前記絶縁膜と前記半導体層とは反対側で界面を形成して接触する電極層とを有し、
前記半導体層と前記絶縁膜の界面における凹凸が、前記絶縁膜と前記電極層との界面における凹凸にそのまま反映されるように、前記絶縁膜の厚さ及び前記両界面の凹凸が形成されていることを特徴とする半導体装置にある。
本発明は上記のような見直しによる知見に鑑みてなされたものである。
これらの酸化の例では、何れも400℃と750℃で行った。
絶縁破壊電圧値は測定したものの中の最小値のものを採用した。
本発明の第1実施形態に係るゲート絶縁膜の模式的断面図を図9に示す。
ここでは、シリコン(Si)を半導体層901として用いた。この半導体基板は、Siウエファーの表面にエピタキシャル法によって半導体層901が形成されたもので、半導体層901表面の面方位は(100)面である。
半導体層901はn型で抵抗率は、10Ω・cmであった。
また、半導体層901の面方位は(100)面に限らない。
次いで、半導体層901の表面を酸化処理して絶縁性酸化膜を形成した。
この様にして、n+型多結晶Siのゲート電極903を形成した。
このようにして作成したゲート絶縁膜903の耐圧特性を測定した。
本発明の第2実施形態に係るゲート絶縁膜の模式的断面図を図13に示す。
半導体層はn型でその抵抗率は10 Ω・cmであった。
熱処理条件は、900℃で1時間であった。
また、熱処理中の圧力は、大気圧よりも低圧としてもよい。
この際のゲート絶縁膜の膜厚は6nmであった。
パターニングされたゲート絶縁膜の絶縁破壊電界強度と破壊確率との関係を図16に示す。図16に示されているように、絶縁破壊電界強度が小さい範囲(即ち、14.5MV/cm以下の範囲)における破壊確率が小さい(ゼロである)ことが分かる。
本発明の第3実施形態に係るMOSトランジスタの断面構造図を図18に示す。ここでは、第1あるいは第2実施形態で説明したゲート絶縁膜を備えているn型チャネルMOSトランジスタについて記載するが、p型チャネルMOSトランジスタであってもよい。
本発明の第4実施形態に係るCMOS回路の模式的断面構造図を図19に示す。
本発明の第5実施形態に係るフローティングゲート型トランジスタからなる半導体メモリの模式的断面図を図20に示す。
更にソース領域2008、ドレイン領域2009をも備えている。
102,502,902,1302,1802,1902a,1902b・・・ゲート絶縁膜
103,503,903,1303,1803,1903a,1903b・・・ゲート電極
104,504,904,1304,1804,1904a,1904b・・・半導体層側界面
105,505,905,1305,1805,1905a,1905b・・・電極側界面
106,506,906,1306・・・・・・半導体層側界面の凹凸
107,507,907,1307・・・・・・電極側界面の凹凸
118,518,918,1318・・・・・・ゲート絶縁膜の膜厚
1800・・・・・・n型チャネルMOSトランジスタ
1808・・・・・・ソース領域
1809・・・・・・ドレイン領域
1900・・・・・・CMOSインバーター回路
1910・・・・・・グラウンド端子
1911・・・・・・電源端子
1912・・・・・・入力端子
1913・・・・・・出力端子
2000・・・・・・半導体メモリ
2014・・・・・・フローティングゲート電極
2015・・・・・・電極間絶縁膜
2016・・・・・・制御ゲート電極
Claims (8)
- 半導体層と、
前記半導体層と界面で形成して接触する絶縁膜と、
前記絶縁膜と前記半導体層とは反対側で界面を形成して接触する電極層と
を有し、
前記半導体層と前記絶縁膜との界面の凹凸の大きさと、前記絶縁膜と前記電極層との界面の凹凸の大きさとが、それぞれ、前記絶縁膜の延在する方向に平行な方向の長さ1μmの領域において、前記絶縁膜の厚さが小さいほどその小ささに対応した小ささであることを特徴とする半導体装置。 - 前記半導体層と前記絶縁膜との界面の凹凸の大きさが前記絶縁膜の厚さの10%以下で、かつ前記絶縁膜と前記電極層との界面の凹凸の大きさが前記絶縁膜の厚さの10%以下であることを特徴とする請求項1に記載の半導体装置。
- 前記両界面の凹凸が、それぞれ前記半導体層の面方位における原子間の最小の段差であることを特徴とする請求項1又は2に記載の半導体装置。
- 半導体層と、
該半導体層上に直に接触している絶縁膜と、
前記半導体層とは反対側で前記絶縁膜と直に接触している電極と、
を有する半導体装置の製造方法であって、
該製造方法の工程中に、
用意した半導体層の表面の凹凸の大きさを、形成される絶縁膜の厚さの10%以下にするための平坦化工程と、
前記半導体層と前記絶縁膜の接する界面の凹凸の大きさと絶縁膜の前記電極を設ける表面の凹凸の大きさがそれぞれ前記形成する絶縁膜の厚さの10%以下になるような酸化、酸窒化または窒化方法によって前記絶縁膜を形成する絶縁膜形成工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記平坦化工程が、
前記半導体層表面の凹凸を、前記半導体層の面方位における原子間の最小の段差にするための平坦化工程を含み、
前記絶縁膜形成工程が、
前記半導体層と前記絶縁膜の接する界面の凹凸の大きさと絶縁膜の前記電極を設ける表面の凹凸の大きさがそれぞれ前記段差の大きさと同等乃至は実質的に同等となるように、酸化、酸窒化または窒化方法によって絶縁膜を形成する工程を含む
請求項4に記載の半導体装置の製造方法。 - 前記平坦化工程は、
水分または酸素の雰囲気、または水分と酸素の混合した雰囲気下において900℃以上の温度で前記用意した半導体層上に酸化膜を形成し、該形成した酸化膜を、フッ酸を含む薬液を用いて除去する工程
を含む請求項4に記載の半導体装置の製造方法。 - 前記平坦化工程は、
前記用意した半導体層は、その表面の自然酸化膜を除去した後に、Ar,H2,Ar/H2のいずれかの雰囲気中において800℃以上の温度で熱処理する工程を含むこと請求項4に記載の半導体装置の製造方法。 - 半導体層と、
該半導体層と直に接触している絶縁膜と、
該絶縁膜と前記半導体層とは反対側で直に接触している電極とを有し、
前記半導体層と前記絶縁膜の界面の凹凸の大きさが、前記絶縁膜と前記電極との界面の凹凸の大きさに反映されるように、前記絶縁膜の厚さ及び前記両界面の凹凸が形成されていることを特徴とする半導体装置。
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