JPS6477950A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6477950A
JPS6477950A JP62235529A JP23552987A JPS6477950A JP S6477950 A JPS6477950 A JP S6477950A JP 62235529 A JP62235529 A JP 62235529A JP 23552987 A JP23552987 A JP 23552987A JP S6477950 A JPS6477950 A JP S6477950A
Authority
JP
Japan
Prior art keywords
bump
metallic film
barrier metallic
film
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235529A
Other languages
Japanese (ja)
Inventor
Nobuo Niwayama
Kazuji Nakajima
Haruhisa Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62235529A priority Critical patent/JPS6477950A/en
Publication of JPS6477950A publication Critical patent/JPS6477950A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Weting (AREA)

Abstract

PURPOSE:To prevent the penetration of an etchant into the lower section of a bump and the occurrence of the peeling of a barrier metallic film by removing an unnecessary barrier metallic film before a bump plating process. CONSTITUTION:A metallic pad 22 having a specified shape and an oxide film 23 with a bump contact window are formed onto a semiconductor substrate 21 and a barrier metallic film 24 onto the whole surface of the semiconductor substrate 21. The unnecessary barrier metallic film 24 except a bump contact section is removed by wet etching through patterning, using a resist film 25 as a mask. Accordingly, since the resist film 25 is employed as the mask, the barrier metallic film 24 is not etched, using a bump 28 as a mask as seen in conventional devices, thus preventing the generation of the penetrating section of an etchant to the lower section of the bump and the peeling section of the barrier metallic film 24, then allowing etching with excellent reproducibility.
JP62235529A 1987-09-18 1987-09-18 Manufacture of semiconductor device Pending JPS6477950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62235529A JPS6477950A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235529A JPS6477950A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6477950A true JPS6477950A (en) 1989-03-23

Family

ID=16987324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235529A Pending JPS6477950A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6477950A (en)

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