JPS645463B2 - - Google Patents
Info
- Publication number
- JPS645463B2 JPS645463B2 JP59171658A JP17165884A JPS645463B2 JP S645463 B2 JPS645463 B2 JP S645463B2 JP 59171658 A JP59171658 A JP 59171658A JP 17165884 A JP17165884 A JP 17165884A JP S645463 B2 JPS645463 B2 JP S645463B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- substrate
- conductivity type
- integrated circuit
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H10P76/40—
-
- H10W10/0148—
-
- H10W10/17—
-
- H10W20/021—
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/083—Ion implantation, general
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/143—Shadow masking
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/561,507 US4584763A (en) | 1983-12-15 | 1983-12-15 | One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation |
| US561507 | 1983-12-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60130134A JPS60130134A (ja) | 1985-07-11 |
| JPS645463B2 true JPS645463B2 (Direct) | 1989-01-30 |
Family
ID=24242263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59171658A Granted JPS60130134A (ja) | 1983-12-15 | 1984-08-20 | 集積回路の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4584763A (Direct) |
| EP (1) | EP0146760B1 (Direct) |
| JP (1) | JPS60130134A (Direct) |
| DE (1) | DE3484846D1 (Direct) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2562326B1 (fr) * | 1984-03-30 | 1987-01-23 | Bois Daniel | Procede de fabrication de zones d'isolation electrique des composants d'un circuit integre |
| US4721682A (en) * | 1985-09-25 | 1988-01-26 | Monolithic Memories, Inc. | Isolation and substrate connection for a bipolar integrated circuit |
| US4700462A (en) * | 1986-10-08 | 1987-10-20 | Hughes Aircraft Company | Process for making a T-gated transistor |
| US4871689A (en) * | 1987-11-17 | 1989-10-03 | Motorola Inc. | Multilayer trench isolation process and structure |
| WO1993016494A1 (en) * | 1992-01-31 | 1993-08-19 | Analog Devices, Inc. | Complementary bipolar polysilicon emitter devices |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3817750A (en) * | 1970-05-05 | 1974-06-18 | Licentia Gmbh | Method of producing a semiconductor device |
| US3909304A (en) * | 1974-05-03 | 1975-09-30 | Western Electric Co | Method of doping a semiconductor body |
| DE2529054C2 (de) * | 1975-06-30 | 1982-04-29 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur Herstellung eines zur Vorlage negativen Resistbildes |
| GB1545208A (en) * | 1975-09-27 | 1979-05-02 | Plessey Co Ltd | Electrical solid state devices |
| US4044452A (en) * | 1976-10-06 | 1977-08-30 | International Business Machines Corporation | Process for making field effect and bipolar transistors on the same semiconductor chip |
| US4196228A (en) * | 1978-06-10 | 1980-04-01 | Monolithic Memories, Inc. | Fabrication of high resistivity semiconductor resistors by ion implanatation |
| US4256514A (en) * | 1978-11-03 | 1981-03-17 | International Business Machines Corporation | Method for forming a narrow dimensioned region on a body |
| US4261763A (en) * | 1979-10-01 | 1981-04-14 | Burroughs Corporation | Fabrication of integrated circuits employing only ion implantation for all dopant layers |
| US4309812A (en) * | 1980-03-03 | 1982-01-12 | International Business Machines Corporation | Process for fabricating improved bipolar transistor utilizing selective etching |
| EP0071665B1 (de) * | 1981-08-08 | 1986-04-16 | Deutsche ITT Industries GmbH | Verfahren zum Herstellen einer monolithisch integrierten Festkörperschaltung mit mindestens einem bipolaren Planartransistor |
| US4472873A (en) * | 1981-10-22 | 1984-09-25 | Fairchild Camera And Instrument Corporation | Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure |
| JPS59920A (ja) * | 1982-06-23 | 1984-01-06 | Fujitsu Ltd | 半導体装置の製造方法 |
| US4498224A (en) * | 1982-12-23 | 1985-02-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of manufacturing a MOSFET using accelerated ions to form an amorphous region |
-
1983
- 1983-12-15 US US06/561,507 patent/US4584763A/en not_active Expired - Fee Related
-
1984
- 1984-08-20 JP JP59171658A patent/JPS60130134A/ja active Granted
- 1984-11-14 EP EP84113732A patent/EP0146760B1/en not_active Expired
- 1984-11-14 DE DE8484113732T patent/DE3484846D1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE3484846D1 (de) | 1991-08-29 |
| US4584763A (en) | 1986-04-29 |
| JPS60130134A (ja) | 1985-07-11 |
| EP0146760A3 (en) | 1989-03-08 |
| EP0146760A2 (en) | 1985-07-03 |
| EP0146760B1 (en) | 1991-07-24 |
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