JPS6443894A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS6443894A
JPS6443894A JP20020087A JP20020087A JPS6443894A JP S6443894 A JPS6443894 A JP S6443894A JP 20020087 A JP20020087 A JP 20020087A JP 20020087 A JP20020087 A JP 20020087A JP S6443894 A JPS6443894 A JP S6443894A
Authority
JP
Japan
Prior art keywords
latch
clk
cycle
port
latches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20020087A
Other languages
English (en)
Inventor
Naoya Ono
Naoki Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20020087A priority Critical patent/JPS6443894A/ja
Publication of JPS6443894A publication Critical patent/JPS6443894A/ja
Pending legal-status Critical Current

Links

Landscapes

  • Read Only Memory (AREA)
  • Dram (AREA)
JP20020087A 1987-08-10 1987-08-10 Semiconductor memory Pending JPS6443894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20020087A JPS6443894A (en) 1987-08-10 1987-08-10 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20020087A JPS6443894A (en) 1987-08-10 1987-08-10 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS6443894A true JPS6443894A (en) 1989-02-16

Family

ID=16420465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20020087A Pending JPS6443894A (en) 1987-08-10 1987-08-10 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS6443894A (ja)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03105788A (ja) * 1989-09-19 1991-05-02 Fujitsu Ltd 半導体記憶装置
EP0695444A1 (en) * 1993-04-22 1996-02-07 Analog Devices, Inc. Multi-phase multi-access pipeline memory system
JPH11232877A (ja) * 1997-07-29 1999-08-27 Motorola Inc パイプライン化デュアルポート集積回路メモリ
JPH11328976A (ja) * 1998-03-20 1999-11-30 Cypress Semiconductor Corp 単一サイクル読み取り／書き込み動作を実施する回路と方法、並びに上記回路を備えて上記方法を実行するランダムアクセスメモリ
JP2000030460A (ja) * 1998-06-23 2000-01-28 Motorola Inc パイプラインド・デュアル・ポ―ト集積回路メモリ
KR100323158B1 (ko) * 1997-10-28 2002-03-08 포만 제프리 엘 다중포트메모리셀을구현하는데이터처리시스템및그구현방법
US6513125B1 (en) 1993-04-22 2003-01-28 Analog Devices, Inc. Multi-phase multi-access pipeline memory system in which the pipeline memory can decode addresses issued by one processor while simultaneously accessing memory array by other processor
JP2011159377A (ja) * 2010-01-29 2011-08-18 Hynix Semiconductor Inc 半導体メモリのデータ出力回路及びその制御方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148692A (ja) * 1984-12-24 1986-07-07 Nippon Telegr & Teleph Corp <Ntt> 記憶装置
JPS6271084A (ja) * 1985-09-21 1987-04-01 Mitsubishi Electric Corp 半導体集積回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148692A (ja) * 1984-12-24 1986-07-07 Nippon Telegr & Teleph Corp <Ntt> 記憶装置
JPS6271084A (ja) * 1985-09-21 1987-04-01 Mitsubishi Electric Corp 半導体集積回路

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03105788A (ja) * 1989-09-19 1991-05-02 Fujitsu Ltd 半導体記憶装置
EP0695444A1 (en) * 1993-04-22 1996-02-07 Analog Devices, Inc. Multi-phase multi-access pipeline memory system
EP0695444A4 (en) * 1993-04-22 2001-09-12 Analog Devices Inc MULTI-PHASE MULTIPLE ACCESS PIPELINE STORAGE SYSTEM
US6513125B1 (en) 1993-04-22 2003-01-28 Analog Devices, Inc. Multi-phase multi-access pipeline memory system in which the pipeline memory can decode addresses issued by one processor while simultaneously accessing memory array by other processor
JPH11232877A (ja) * 1997-07-29 1999-08-27 Motorola Inc パイプライン化デュアルポート集積回路メモリ
KR100323158B1 (ko) * 1997-10-28 2002-03-08 포만 제프리 엘 다중포트메모리셀을구현하는데이터처리시스템및그구현방법
JPH11328976A (ja) * 1998-03-20 1999-11-30 Cypress Semiconductor Corp 単一サイクル読み取り／書き込み動作を実施する回路と方法、並びに上記回路を備えて上記方法を実行するランダムアクセスメモリ
JP2000030460A (ja) * 1998-06-23 2000-01-28 Motorola Inc パイプラインド・デュアル・ポ―ト集積回路メモリ
JP2011159377A (ja) * 2010-01-29 2011-08-18 Hynix Semiconductor Inc 半導体メモリのデータ出力回路及びその制御方法

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