JPS6432675A - Method of forming insulated island on silicon substrate - Google Patents
Method of forming insulated island on silicon substrateInfo
- Publication number
- JPS6432675A JPS6432675A JP63102841A JP10284188A JPS6432675A JP S6432675 A JPS6432675 A JP S6432675A JP 63102841 A JP63102841 A JP 63102841A JP 10284188 A JP10284188 A JP 10284188A JP S6432675 A JPS6432675 A JP S6432675A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- heavily doped
- processing
- apply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/043,510 US4810667A (en) | 1987-04-28 | 1987-04-28 | Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6432675A true JPS6432675A (en) | 1989-02-02 |
Family
ID=21927524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63102841A Pending JPS6432675A (en) | 1987-04-28 | 1988-04-27 | Method of forming insulated island on silicon substrate |
Country Status (2)
Country | Link |
---|---|
US (1) | US4810667A (ja) |
JP (1) | JPS6432675A (ja) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4982263A (en) * | 1987-12-21 | 1991-01-01 | Texas Instruments Incorporated | Anodizable strain layer for SOI semiconductor structures |
US5332920A (en) * | 1988-02-08 | 1994-07-26 | Kabushiki Kaisha Toshiba | Dielectrically isolated high and low voltage substrate regions |
US4910165A (en) * | 1988-11-04 | 1990-03-20 | Ncr Corporation | Method for forming epitaxial silicon on insulator structures using oxidized porous silicon |
US5057022A (en) * | 1989-03-20 | 1991-10-15 | Miller Robert O | Method of making a silicon integrated circuit waveguide |
US4927781A (en) * | 1989-03-20 | 1990-05-22 | Miller Robert O | Method of making a silicon integrated circuit waveguide |
US5049521A (en) * | 1989-11-30 | 1991-09-17 | Silicon General, Inc. | Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate |
US5110755A (en) * | 1990-01-04 | 1992-05-05 | Westinghouse Electric Corp. | Process for forming a component insulator on a silicon substrate |
US5043292A (en) * | 1990-05-31 | 1991-08-27 | National Semiconductor Corporation | Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures |
US5049513A (en) * | 1990-09-17 | 1991-09-17 | Texas Instruments Incorporated | Bi CMOS/SOI process flow |
US5135884A (en) * | 1991-03-28 | 1992-08-04 | Sgs-Thomson Microelectronics, Inc. | Method of producing isoplanar isolated active regions |
US5561073A (en) * | 1992-03-13 | 1996-10-01 | Jerome; Rick C. | Method of fabricating an isolation trench for analog bipolar devices in harsh environments |
US5344785A (en) * | 1992-03-13 | 1994-09-06 | United Technologies Corporation | Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate |
US5372952A (en) * | 1992-04-03 | 1994-12-13 | National Semiconductor Corporation | Method for forming isolated semiconductor structures |
US5217920A (en) * | 1992-06-18 | 1993-06-08 | Motorola, Inc. | Method of forming substrate contact trenches and isolation trenches using anodization for isolation |
US5306659A (en) * | 1993-03-29 | 1994-04-26 | International Business Machines Corporation | Reach-through isolation etching method for silicon-on-insulator devices |
US5420049A (en) * | 1993-09-09 | 1995-05-30 | The United States Of America As Represented By The Secretary Of The Navy | Method of controlling photoemission from porous silicon using ion implantation |
JPH07176608A (ja) * | 1993-12-17 | 1995-07-14 | Nec Corp | 半導体装置およびその製造方法 |
JPH0864674A (ja) * | 1994-08-04 | 1996-03-08 | Lg Semicon Co Ltd | 半導体素子の絶縁方法 |
KR0160542B1 (ko) * | 1994-12-15 | 1999-02-01 | 정선종 | 모노리틱 마이크로 웨이브 집적회로용 기판 및 그 제조방법 |
US5741737A (en) * | 1996-06-27 | 1998-04-21 | Cypress Semiconductor Corporation | MOS transistor with ramped gate oxide thickness and method for making same |
US5897354A (en) * | 1996-12-17 | 1999-04-27 | Cypress Semiconductor Corporation | Method of forming a non-volatile memory device with ramped tunnel dielectric layer |
US6891213B1 (en) | 1999-03-16 | 2005-05-10 | Micron Technology, Inc. | Base current reversal SRAM memory cell and method |
US6313490B1 (en) | 1999-03-16 | 2001-11-06 | Micron Technology, Inc. | Base current reversal SRAM memory cell and method |
KR100311496B1 (ko) * | 1999-08-16 | 2001-10-18 | 김영환 | 불휘발성 강유전체 메모리 장치 및 그 제조방법 |
US20040048437A1 (en) * | 2002-09-11 | 2004-03-11 | Dubin Valery M. | Method of making oxide embedded transistor structures |
FR2845522A1 (fr) * | 2002-10-03 | 2004-04-09 | St Microelectronics Sa | Circuit integre a couche enterree fortement conductrice |
US8829332B1 (en) | 2013-03-14 | 2014-09-09 | Tower Semiconductor Ltd. | Photovoltaic device formed on porous silicon isolation |
US8828781B1 (en) | 2013-03-14 | 2014-09-09 | Tower Semiconductor Ltd. | Method for producing photovoltaic device isolated by porous silicon |
US10796942B2 (en) | 2018-08-20 | 2020-10-06 | Stmicroelectronics S.R.L. | Semiconductor structure with partially embedded insulation region |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53105988A (en) * | 1977-02-24 | 1978-09-14 | Ibm | Method of forming completely separated dielectric region |
JPS61180446A (ja) * | 1984-10-31 | 1986-08-13 | テキサス インスツルメンツ インコ−ポレイテツド | 分離されたn型エピタキシヤルアイランドの形成方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3944447A (en) * | 1973-03-12 | 1976-03-16 | Ibm Corporation | Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation |
US4643804A (en) * | 1985-07-25 | 1987-02-17 | At&T Bell Laboratories | Forming thick dielectric at the bottoms of trenches utilized in integrated-circuit devices |
-
1987
- 1987-04-28 US US07/043,510 patent/US4810667A/en not_active Expired - Lifetime
-
1988
- 1988-04-27 JP JP63102841A patent/JPS6432675A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53105988A (en) * | 1977-02-24 | 1978-09-14 | Ibm | Method of forming completely separated dielectric region |
JPS61180446A (ja) * | 1984-10-31 | 1986-08-13 | テキサス インスツルメンツ インコ−ポレイテツド | 分離されたn型エピタキシヤルアイランドの形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US4810667A (en) | 1989-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6432675A (en) | Method of forming insulated island on silicon substrate | |
JPS6459866A (en) | Manufacture of mos transistor | |
JPS5795625A (en) | Manufacture of semiconductor device | |
JPS54146584A (en) | Manufacture of semiconductor device | |
JPS57208124A (en) | Manufacture of semiconductor device | |
TW362259B (en) | Method for forming an isolation region in a semiconductor device and resulting structure | |
JPS575328A (en) | Growing method for semiconductor crystal | |
JPS5763842A (en) | Preparation of semiconductor integrated circuit | |
JPS5756942A (en) | Manufacture of silicon semiconductor device | |
JPS6457641A (en) | Manufacture of semiconductor device | |
JPS5688356A (en) | Manufacture of memory cell | |
JPS5687339A (en) | Manufacture of semiconductor device | |
JPS5512735A (en) | Semiconductor device | |
JPS6435958A (en) | Thin film transistor | |
JPS562547A (en) | Electric field effect semiconductor ion sensor | |
JPS57113250A (en) | Semiconductor device | |
JPS56104468A (en) | Manufacture of mos semiconductor device | |
JPS57128943A (en) | Insulation isolated semiconductor integrated device and manufacture thereof | |
JPS56125846A (en) | Surface treatment of semiconductor | |
JPS5681969A (en) | Manufacture of semiconductor device | |
JPS5429587A (en) | Semiconductor device | |
JPS52130575A (en) | Semiconductor device and its preparation | |
JPS5662370A (en) | Manufacturing of semiconductor device | |
JPS5323574A (en) | Forming method of silicon oxide film | |
JPS553650A (en) | Semiconductor device production |