JPS6412092B2 - - Google Patents

Info

Publication number
JPS6412092B2
JPS6412092B2 JP55018136A JP1813680A JPS6412092B2 JP S6412092 B2 JPS6412092 B2 JP S6412092B2 JP 55018136 A JP55018136 A JP 55018136A JP 1813680 A JP1813680 A JP 1813680A JP S6412092 B2 JPS6412092 B2 JP S6412092B2
Authority
JP
Japan
Prior art keywords
solder
electrode
electrode plate
cathode
cutout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55018136A
Other languages
English (en)
Other versions
JPS56115542A (en
Inventor
Toshuki Fujii
Takashi Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1813680A priority Critical patent/JPS56115542A/ja
Publication of JPS56115542A publication Critical patent/JPS56115542A/ja
Publication of JPS6412092B2 publication Critical patent/JPS6412092B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 この発明は半導体ペレツト上にろう材を介して
電極取り出し金属板を固着して組立てた半導体装
置の改良に関するものである。
半導体ペレツトをはんだ等のろう材で組立基体
に接続固着させた構造は、ワイヤボンデイング構
造とは別に、特に中電力半導体装置に広く用いら
れている。
以下サイリスタの場合を例にとつて説明する。
第１図はこの発明の適用対象である半導体装置
の組立構造を示す分解斜視図である。図におい
て、１００は４mm角のサイリスタペレツト、１は
そのゲート電極、２はカソード電極、３は0.2mm
厚のゲート電極板、４は0.2mm厚のカソード電極
板、５はゲート電極１とゲート電極板３との間、
およびカソード電極２とカソード電極板４との間
を固着接続するための３mm角、0.07mm厚の一枚の
成形はんだで、これはゲート電極１の上とカソー
ド電極２の上とに別個に載置されていたものを１
個の成形はんだでおきかえて、組立の部品点数を
減少させるようにしたものである。２００はリー
ドフレーム６はそのアノードリード端、７はゲー
トリード端、８はカソードリード端である。９は
ゲート電極板３とリードフレーム２００のゲート
リード端７とを固着接続するためのはんだ、１０
はカソード電極板４とリードフレーム２００のカ
ソードリード端８とを固着接続するためのはん
だ、１１はサイリスタペレツト１００の下面のア
ノード電極（図示せず）とリードフレーム２００
のアノードリード端６とを固着接続するためのは
んだである。
上記各部材は治具内に所要順序に組込んで350
℃程度の温度の炉ではんだ付けがなされた後に術
脂封止され、リードフレーム２００の不要部分は
切除されて第２図に斜視図で示すサイリスタが完
成する。第２図において、１２は封止樹脂であ
る。
ところで、このような、ゲート電極１とカソー
ド電極２とをそれぞれの電極板３および４に固着
接続するために共通の１枚の成形はんだ５を用い
る方式では、上述の半田付け工程で、第３図に拡
大斜視図で示すように、１枚のはんだ５が溶融し
て、メタライズの施されたゲート電極１とカソー
ド電極２とに分離してはんだ付けが完成するのが
普通である。
しかし、成形はんだ５がゲート電極１側へずれ
て配置されたり、ゲート電極板３およびカソード
電極板４が成形はんだ５の表面から浮き上つて配
置された状態ではんだ付け工程が実行されると、
成形はんだ５がゲート電極１とカソード電極２と
に分離せずに、両電極１および２をブリツジし
て、電気的に短絡してサイリスタが機能を発揮し
ないことがある。第４図はこのようにブリツジ現
象を生じた状態を示す要部拡大斜視図で、１３は
このブリツジ部分を示す。このブリツジ現象はは
んだ付けの昇温時に溶融したはんだ５の表面張力
が、はんだ５とゲート電極１およびカソード電極
２のメタライズ層との界面張力よりも大きくなつ
て、両電極間の中間部にはんだがとり残されて生
じるものである。
この発明は以上のような点に鑑みてなされたも
ので、半導体ペレツトの一つの主面上に並んで形
成された複数のメタライズ電極上にそれぞれこれ
らとほぼ同形の電極板を共通の１枚の成形はんだ
を用いてはんだ付けする際に、はんだによる電極
間のブリツジ現象が生じないようにした半導体装
置を提供することを目的としている。
第５図はこの発明の一実施例の要部を示す拡大
斜視図で、従来例と同等部分は同一符号で示し、
その説明を省略する。そして本実施例では、図示
のように、カソード電極板４の周縁の、ゲート電
極１に対向する中央部に半径0.4mm程度の切り欠
き１４を設けている。この切り欠き１４部は、従
来はんだ付け時に電極板間のブリツジを形成して
いた余剰のはんだをここに吸い取つて溜めること
によつて、ゲート・カソード間の電気的短絡の発
生を防止するためのものである。すなわち、はん
だ付け条件の「ばらつき」に伴うはんだ分離の不
整を、はんだの流れ方を強制することによつて解
決しようとするものである。
なお上記実施例ではサイリスタについて述べた
が、この発明はこれ以外の一般の半導体装置にも
適用できる。また、電極板に設けるはんだ溜め用
切り欠きは必ずしも対向電極板の対向中央部に設
ける必要はない。
以上詳述したように、この発明では半導体ペレ
ツトの一主面上に形成された複数のメタライズ電
極領域にそれぞれはんだ付けされる電極板のはん
だ付け部の互いに対向する少くとも一方の周縁の
一部に切り欠きを設けたので、上記半導体ペレツ
トの上記一主面上に上記複数のメタライズ電極領
域を覆う大きさの一枚の成形はんだを挾んで上記
各メタライズ電極領域に対向して上記電極板を載
置し、昇温させて上記各メタライズ電極領域にそ
れぞれ電極板をはんだ付けした時、余剰のはんだ
は上記切り欠きの部位に吸い取られ、これにより
上記電極板間のはんだによるブリツジの発生を防
止できる効果がある。
【図面の簡単な説明】
第１図はこの発明の適用対象である半導体装置
の組立て構造を示す分解斜視図、第２図は組み立
て後樹脂封止した半導体装置を示す斜視図、第３
図はそのはんだ付け組み立て状態を示す拡大斜視
図、第４図は従来の電極板間のはんだブリツジの
発生状況を示す要部拡大斜視図、第５図はこの発
明の一実施例の要部を示す拡大斜視図である。 図において、１００はサイリスタ（半導体）ペ
レツト、２００はリードフレーム、１はゲート電
極、２はカソード電極、３はゲート電極板、４は
カソード電極板、５は成形はんだ、１３ははんだ
ブリツジ部分、１４は切欠きである。なお、図中
同一符号は同一または相当部分を示す。

Claims (1)

    【特許請求の範囲】
  1. １ 一主面上に複数のメタライズ電極領域が形成
    された半導体ペレツトと、上記各メタライズ電極
    領域とほぼ同じ形状のはんだ付け部分を有し上記
    はんだ付け部分がそれぞれ上記各メタライズ電極
    領域上にはんだ付けされる電極板とを備え、上記
    半導体ペレツトの上記一主面上に上記複数のメタ
    ライズ電極領域を覆う大きさの一枚の成形はんだ
    を挾んで上記各メタライズ電極領域に対応する上
    記電極板を載置し、昇温により上記一枚の成形は
    んだを上記複数のメタライズ電極領域毎に分離し
    て上記各電極板をはんだ付けしてなる半導体装置
    において、上記電極板のはんだ付け部分の互いに
    対向する少なくとも一方の周縁の一部に余剰はん
    だを吸い取るための切り欠きを設けたことを特徴
    とする半導体装置。
JP1813680A 1980-02-16 1980-02-16 Semiconductor device Granted JPS56115542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1813680A JPS56115542A (en) 1980-02-16 1980-02-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1813680A JPS56115542A (en) 1980-02-16 1980-02-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS56115542A JPS56115542A (en) 1981-09-10
JPS6412092B2 true JPS6412092B2 (ja) 1989-02-28

Family

ID=11963179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1813680A Granted JPS56115542A (en) 1980-02-16 1980-02-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56115542A (ja)

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JP2006324320A (ja) * 2005-05-17 2006-11-30 Renesas Technology Corp 半導体装置
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