JPS641057B2 - - Google Patents
Info
- Publication number
- JPS641057B2 JPS641057B2 JP57168402A JP16840282A JPS641057B2 JP S641057 B2 JPS641057 B2 JP S641057B2 JP 57168402 A JP57168402 A JP 57168402A JP 16840282 A JP16840282 A JP 16840282A JP S641057 B2 JPS641057 B2 JP S641057B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- base metal
- wiring pattern
- wiring board
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H10W70/611—
-
- H10W70/685—
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
-
- H10W72/5449—
-
- H10W72/5522—
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- H10W90/754—
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168402A JPS5958848A (ja) | 1982-09-29 | 1982-09-29 | セラミツク配線基板の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168402A JPS5958848A (ja) | 1982-09-29 | 1982-09-29 | セラミツク配線基板の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5958848A JPS5958848A (ja) | 1984-04-04 |
| JPS641057B2 true JPS641057B2 (enExample) | 1989-01-10 |
Family
ID=15867450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57168402A Granted JPS5958848A (ja) | 1982-09-29 | 1982-09-29 | セラミツク配線基板の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5958848A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3225854B2 (ja) * | 1996-10-02 | 2001-11-05 | 株式会社デンソー | 厚膜回路基板及びそのワイヤボンディング電極形成方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940867A (enExample) * | 1972-08-25 | 1974-04-17 | ||
| JPS6041859B2 (ja) * | 1980-02-13 | 1985-09-19 | 三菱電機株式会社 | 半導体容器 |
| JPS57130443A (en) * | 1981-02-06 | 1982-08-12 | Nec Corp | Substrate for hybrid integrated circuit |
-
1982
- 1982-09-29 JP JP57168402A patent/JPS5958848A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5958848A (ja) | 1984-04-04 |
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