JPS639708B2 - - Google Patents

Info

Publication number
JPS639708B2
JPS639708B2 JP8566581A JP8566581A JPS639708B2 JP S639708 B2 JPS639708 B2 JP S639708B2 JP 8566581 A JP8566581 A JP 8566581A JP 8566581 A JP8566581 A JP 8566581A JP S639708 B2 JPS639708 B2 JP S639708B2
Authority
JP
Japan
Prior art keywords
transmission
signal
transmission line
speed
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8566581A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57201934A (en
Inventor
Masao Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP8566581A priority Critical patent/JPS57201934A/ja
Publication of JPS57201934A publication Critical patent/JPS57201934A/ja
Publication of JPS639708B2 publication Critical patent/JPS639708B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bidirectional Digital Transmission (AREA)
  • Communication Control (AREA)
JP8566581A 1981-06-05 1981-06-05 Memory switching system of buffer circuit Granted JPS57201934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8566581A JPS57201934A (en) 1981-06-05 1981-06-05 Memory switching system of buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8566581A JPS57201934A (en) 1981-06-05 1981-06-05 Memory switching system of buffer circuit

Publications (2)

Publication Number Publication Date
JPS57201934A JPS57201934A (en) 1982-12-10
JPS639708B2 true JPS639708B2 (enrdf_load_stackoverflow) 1988-03-01

Family

ID=13865112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8566581A Granted JPS57201934A (en) 1981-06-05 1981-06-05 Memory switching system of buffer circuit

Country Status (1)

Country Link
JP (1) JPS57201934A (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134687A (ja) * 1983-12-23 1985-07-17 Mitsubishi Corp テレビ会議電話装置
JPH0773274B2 (ja) * 1985-06-04 1995-08-02 株式会社日立製作所 伝送装置端末のアドレス判定回路
JP2578788B2 (ja) * 1987-01-05 1997-02-05 沖電気工業株式会社 １心双方向時分割光伝送装置
JPH0630513B2 (ja) * 1987-03-27 1994-04-20 横河電機株式会社 デ−タ伝送バツフア回路
JP2769418B2 (ja) * 1993-01-22 1998-06-25 国際電気株式会社 バッファ及びそのデータ変換方法

Also Published As

Publication number Publication date
JPS57201934A (en) 1982-12-10

Similar Documents

Publication Publication Date Title
US4047246A (en) I/O bus transceiver for a data processing system
US5717948A (en) Interface circuit associated with a processor to exchange digital data in series with a peripheral device
US3814860A (en) Scanning technique for multiplexer apparatus
JPS639708B2 (enrdf_load_stackoverflow)
US5197065A (en) Distribution mechanism for establishing communications between user interfaces of a communication system
US4047201A (en) I/O Bus transceiver for a data processing system
NL9002426A (nl) Elastisch buffergeheugen.
US3898387A (en) Digital data switching system utilizing voice encoding and decoding circuitry
JPS62500555A (ja) デジタル装置を時間多重リンクに接続するためのインタフエ−ス回路
ES429114A1 (es) Perfeccionamientos introducidos en una central de transito para la transmision de senales de datos asincronas.
SU1647572A1 (ru) Устройство дл контрол последовательного кода
JPS586345B2 (ja) フクゴウカソウチ
SU471583A1 (ru) Устройство дл передачи информации из цифровой вычислительной машины в линию св зи
SU1667088A1 (ru) Устройство дл сопр жени абонента с каналом св зи
SU1144113A1 (ru) Устройство дл сопр жени двух вычислительных машин
RU1835545C (ru) Устройство обмена информацией между ЭВМ и абонентами
US4187402A (en) Method of controlling channel assignment in a time division multiplexing network
JP3138597B2 (ja) バースト信号送出管理用メモリを用いたダイナミックポーリング方式
SU1012235A1 (ru) Устройство дл обмена данными
SU1267397A1 (ru) Устройство дл ввода-вывода информации
SU662928A1 (ru) Устройство дл сопр жени каналов св зи с цифровой вычислительной машиной
SU1305700A1 (ru) Устройство дл сопр жени абонентов с цифровой вычислительной машиной
SU1262510A1 (ru) Устройство дл сопр жени абонентов с каналами св зи
SU777655A1 (ru) Устройство дл сопр жени
RU1837302C (ru) Устройство дл сопр жени ЭВМ с разноскоростными группами внешних устройств