JPS54145442A - Buffer control system - Google Patents

Buffer control system

Info

Publication number
JPS54145442A
JPS54145442A JP5371678A JP5371678A JPS54145442A JP S54145442 A JPS54145442 A JP S54145442A JP 5371678 A JP5371678 A JP 5371678A JP 5371678 A JP5371678 A JP 5371678A JP S54145442 A JPS54145442 A JP S54145442A
Authority
JP
Japan
Prior art keywords
write
buffer
line
addressing
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5371678A
Other languages
Japanese (ja)
Inventor
Eiichi Adachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP5371678A priority Critical patent/JPS54145442A/en
Publication of JPS54145442A publication Critical patent/JPS54145442A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To enable a system to cope rapidly with a change in the number of bits per line due to a change in original size, by addressing to a buffer memory by an up-down counter. CONSTITUTION:Line buffers 10 and 11 are provided, which have the data capacity for one line in the main scanning direction of a transmitting original, and are alternated for a write and a read. In a transmission mode first, pattern information read out from the transmitting original is sent to buffer 10 via line 2 and up-down counter 12 receives clock pulse CLK1 at its up terminal and counts up it, thereby assigning addresses in sequence. After a write for one line ends, a read starts at the same time as a write to buffer 11 in the reverse addressing order, resulting from that counter 12 receives clock pulse CLK2. In a reception mode, on the other hand, a write to and a red from buffer 10 are carried out in the addressing order reverse to that in the transmission mode.
JP5371678A 1978-05-08 1978-05-08 Buffer control system Pending JPS54145442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5371678A JPS54145442A (en) 1978-05-08 1978-05-08 Buffer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5371678A JPS54145442A (en) 1978-05-08 1978-05-08 Buffer control system

Publications (1)

Publication Number Publication Date
JPS54145442A true JPS54145442A (en) 1979-11-13

Family

ID=12950545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5371678A Pending JPS54145442A (en) 1978-05-08 1978-05-08 Buffer control system

Country Status (1)

Country Link
JP (1) JPS54145442A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5886634A (en) * 1981-11-17 1983-05-24 Ricoh Co Ltd Controller for buffer memory
JPS6395775A (en) * 1986-10-09 1988-04-26 Konica Corp Picture processing unit capable of magnifying and reducing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5886634A (en) * 1981-11-17 1983-05-24 Ricoh Co Ltd Controller for buffer memory
JPS6395775A (en) * 1986-10-09 1988-04-26 Konica Corp Picture processing unit capable of magnifying and reducing
JPH0567106B2 (en) * 1986-10-09 1993-09-24 Konishiroku Photo Ind

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